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These architectures use a simplified firmware boot sequence: FMC --> FSP --> GSP, with no SEC2 involvement. This commit adds the ability to wait for FSP secure boot completion by polling the I2CS thermal scratch register until FSP signals success. Signed-off-by: John Hubbard --- drivers/gpu/nova-core/fsp.rs | 183 +++++++++++++++++++++++++++++ drivers/gpu/nova-core/nova_core.rs | 1 + 2 files changed, 184 insertions(+) create mode 100644 drivers/gpu/nova-core/fsp.rs diff --git a/drivers/gpu/nova-core/fsp.rs b/drivers/gpu/nova-core/fsp.rs new file mode 100644 index 000000000000..12529b139861 --- /dev/null +++ b/drivers/gpu/nova-core/fsp.rs @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: GPL-2.0 + +// TODO: remove this once the code is fully functional +#![expect(dead_code)] + +//! FSP (Firmware System Processor) interface for Hopper/Blackwell GPUs. +//! +//! Hopper/Blackwell use a simplified firmware boot sequence: FMC --> FSP --> GSP. +//! Unlike Turing/Ampere/Ada, there is NO SEC2 (Security Engine 2) usage. +//! FSP handles secure boot directly using FMC firmware + Chain of Trust. + +use kernel::{ + device, + io::poll::read_poll_timeout, + prelude::*, + time::Delta, + transmute::{ + AsBytes, + FromBytes, // + }, +}; + +use crate::regs::FSP_BOOT_COMPLETE_SUCCESS; + +/// FSP secure boot completion timeout in milliseconds. +const FSP_SECURE_BOOT_TIMEOUT_MS: i64 = 4000; + +/// MCTP (Management Component Transport Protocol) header values for FSP communication. +pub(crate) mod mctp { + pub(super) const HEADER_SOM: u32 = 1; // Start of Message + pub(super) const HEADER_EOM: u32 = 1; // End of Message + pub(super) const HEADER_SEID: u32 = 0; // Source Endpoint ID + pub(super) const HEADER_SEQ: u32 = 0; // Sequence number + + pub(super) const MSG_TYPE_VENDOR_PCI: u32 = 0x7e; + pub(super) const VENDOR_ID_NV: u32 = 0x10de; + pub(super) const NVDM_TYPE_COT: u32 = 0x14; + pub(super) const NVDM_TYPE_FSP_RESPONSE: u32 = 0x15; +} + +/// GSP FMC boot parameters structure. +/// This is what FSP expects to receive for booting GSP-RM. +/// GSP FMC initialization parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspFmcInitParams { + /// CC initialization "registry keys" + regkeys: u32, +} + +// SAFETY: GspFmcInitParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspFmcInitParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspFmcInitParams {} + +/// GSP ACR (Authenticated Code RAM) boot parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspAcrBootGspRmParams { + /// Physical memory aperture through which gspRmDescPa is accessed + target: u32, + /// Size in bytes of the GSP-RM descriptor structure + gsp_rm_desc_size: u32, + /// Physical offset in the target aperture of the GSP-RM descriptor structure + gsp_rm_desc_offset: u64, + /// Physical offset in FB to set the start of the WPR containing GSP-RM + wpr_carveout_offset: u64, + /// Size in bytes of the WPR containing GSP-RM + wpr_carveout_size: u32, + /// Whether to boot GSP-RM or GSP-Proxy through ACR + b_is_gsp_rm_boot: u32, +} + +// SAFETY: GspAcrBootGspRmParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspAcrBootGspRmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspAcrBootGspRmParams {} + +/// GSP RM boot parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspRmParams { + /// Physical memory aperture through which bootArgsOffset is accessed + target: u32, + /// Physical offset in the memory aperture that will be passed to GSP-RM + boot_args_offset: u64, +} + +// SAFETY: GspRmParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspRmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspRmParams {} + +/// GSP SPDM (Security Protocol and Data Model) parameters. +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +struct GspSpdmParams { + /// Physical Memory Aperture through which all addresses are accessed + target: u32, + /// Physical offset in the memory aperture where SPDM payload buffer is stored + payload_buffer_offset: u64, + /// Size of the above payload buffer + payload_buffer_size: u32, +} + +// SAFETY: GspSpdmParams is a simple C struct with only primitive types. +unsafe impl AsBytes for GspSpdmParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspSpdmParams {} + +/// Complete GSP FMC boot parameters structure. +/// This is what FSP expects to receive - NOT a raw libos address! +#[repr(C)] +#[derive(Debug, Clone, Copy, Default)] +pub(crate) struct GspFmcBootParams { + init_params: GspFmcInitParams, + boot_gsp_rm_params: GspAcrBootGspRmParams, + gsp_rm_params: GspRmParams, + gsp_spdm_params: GspSpdmParams, +} + +// SAFETY: GspFmcBootParams is composed of C structs with only primitive types. +unsafe impl AsBytes for GspFmcBootParams {} +// SAFETY: All bit patterns are valid for the primitive fields. +unsafe impl FromBytes for GspFmcBootParams {} + +/// FSP interface for Hopper/Blackwell GPUs. +pub(crate) struct Fsp; + +impl Fsp { + /// Wait for FSP secure boot completion. + /// + /// Polls the thermal scratch register until FSP signals boot completion + /// or timeout occurs. + pub(crate) fn wait_secure_boot( + dev: &device::Device, + bar: &crate::driver::Bar0, + arch: crate::gpu::Architecture, + ) -> Result<()> { + let timeout = Delta::from_millis(FSP_SECURE_BOOT_TIMEOUT_MS); + + // Check if this architecture supports FSP thermal scratch register + let initial_status = + crate::regs::read_fsp_boot_complete_status(bar, arch).inspect_err(|_| { + dev_err!( + dev, + "FSP thermal scratch register not supported for architecture {:?}\n", + arch + ) + })?; + dev_dbg!( + dev, + "FSP initial I2CS scratch register status: {:#x}\n", + initial_status + ); + + read_poll_timeout( + || crate::regs::read_fsp_boot_complete_status(bar, arch), + |&status| { + dev_dbg!( + dev, + "FSP I2CS scratch register status: {:#x} (expected: {:#x})\n", + status, + FSP_BOOT_COMPLETE_SUCCESS + ); + status == FSP_BOOT_COMPLETE_SUCCESS + }, + Delta::ZERO, + timeout, + ) + .map_err(|_| { + let final_status = + crate::regs::read_fsp_boot_complete_status(bar, arch).unwrap_or(0xDEADBEEF); + dev_err!( + dev, + "FSP secure boot completion timeout - final status: {:#x}\n", + final_status + ); + ETIMEDOUT + }) + .map(|_| ()) + } +} diff --git a/drivers/gpu/nova-core/nova_core.rs b/drivers/gpu/nova-core/nova_core.rs index b98a1c03f13d..5a8f52cebfff 100644 --- a/drivers/gpu/nova-core/nova_core.rs +++ b/drivers/gpu/nova-core/nova_core.rs @@ -10,6 +10,7 @@ mod falcon; mod fb; mod firmware; +mod fsp; mod gfw; mod gpu; mod gsp; -- 2.52.0