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dkim=none (message not signed) header.d=none;dmarc=pass action=none header.from=nvidia.com; Received-SPF: Pass (protection.outlook.com: domain of nvidia.com designates 216.228.117.160 as permitted sender) receiver=protection.outlook.com; client-ip=216.228.117.160; helo=mail.nvidia.com; pr=C Received: from mail.nvidia.com (216.228.117.160) by BL6PEPF00022572.mail.protection.outlook.com (10.167.249.40) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9499.1 via Frontend Transport; Sat, 3 Jan 2026 04:59:59 +0000 Received: from rnnvmail201.nvidia.com (10.129.68.8) by mail.nvidia.com (10.129.200.66) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 2 Jan 2026 20:59:52 -0800 Received: from ubuntu (10.126.231.35) by rnnvmail201.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.20; Fri, 2 Jan 2026 20:59:51 -0800 From: Timur Tabi To: Danilo Krummrich , Alexandre Courbot , Joel Fernandes , John Hubbard , , Subject: [PATCH v5 07/11] gpu: nova-core: Add basic Turing HAL Date: Fri, 2 Jan 2026 22:59:30 -0600 Message-ID: <20260103045934.64521-8-ttabi@nvidia.com> X-Mailer: git-send-email 2.51.0 In-Reply-To: <20260103045934.64521-1-ttabi@nvidia.com> References: <20260103045934.64521-1-ttabi@nvidia.com> Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: rnnvmail201.nvidia.com (10.129.68.8) To rnnvmail201.nvidia.com (10.129.68.8) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF00022572:EE_|SJ2PR12MB8874:EE_ X-MS-Office365-Filtering-Correlation-Id: 98a17e98-1c31-41dc-ea1c-08de4a84f267 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700013|1800799024|82310400026; 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X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Jan 2026 04:59:59.4467 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 98a17e98-1c31-41dc-ea1c-08de4a84f267 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF00022572.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ2PR12MB8874 Add the basic HAL for recognizing Turing GPUs. This isn't enough to support booting GSP-RM on Turing, but it's a start. Note that GA100, which boots using the same method as Turing, is not supported yet. Signed-off-by: Timur Tabi Reviewed-by: John Hubbard --- drivers/gpu/nova-core/falcon/hal.rs | 4 ++ drivers/gpu/nova-core/falcon/hal/tu102.rs | 79 +++++++++++++++++++++++ drivers/gpu/nova-core/regs.rs | 14 ++++ 3 files changed, 97 insertions(+) create mode 100644 drivers/gpu/nova-core/falcon/hal/tu102.rs diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/falcon/hal.rs index c77a1568ea96..c886ba03d1f6 100644 --- a/drivers/gpu/nova-core/falcon/hal.rs +++ b/drivers/gpu/nova-core/falcon/hal.rs @@ -13,6 +13,7 @@ }; mod ga102; +mod tu102; /// Hardware Abstraction Layer for Falcon cores. /// @@ -60,6 +61,9 @@ pub(super) fn falcon_hal( use Chipset::*; let hal = match chipset { + TU102 | TU104 | TU106 | TU116 | TU117 => { + KBox::new(tu102::Tu102::::new(), GFP_KERNEL)? as KBox> + } GA102 | GA103 | GA104 | GA106 | GA107 | AD102 | AD103 | AD104 | AD106 | AD107 => { KBox::new(ga102::Ga102::::new(), GFP_KERNEL)? as KBox> } diff --git a/drivers/gpu/nova-core/falcon/hal/tu102.rs b/drivers/gpu/nova-core/falcon/hal/tu102.rs new file mode 100644 index 000000000000..586d5dc6b417 --- /dev/null +++ b/drivers/gpu/nova-core/falcon/hal/tu102.rs @@ -0,0 +1,79 @@ +// SPDX-License-Identifier: GPL-2.0 + +use core::marker::PhantomData; + +use kernel::{ + io::poll::read_poll_timeout, + prelude::*, + time::delay::fsleep, + time::Delta, // +}; + +use crate::{ + driver::Bar0, + falcon::{ + Falcon, + FalconBromParams, + FalconEngine, // + }, + regs, // +}; + +use super::FalconHal; + +pub(super) struct Tu102(PhantomData); + +impl Tu102 { + pub(super) fn new() -> Self { + Self(PhantomData) + } +} + +impl FalconHal for Tu102 { + fn select_core(&self, _falcon: &Falcon, _bar: &Bar0) -> Result { + Ok(()) + } + + fn signature_reg_fuse_version( + &self, + _falcon: &Falcon, + _bar: &Bar0, + _engine_id_mask: u16, + _ucode_id: u8, + ) -> Result { + Ok(0) + } + + fn program_brom(&self, _falcon: &Falcon, _bar: &Bar0, _params: &FalconBromParams) -> Result { + Ok(()) + } + + fn is_riscv_active(&self, bar: &Bar0) -> bool { + let cpuctl = regs::NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS::read(bar, &E::ID); + cpuctl.active_stat() + } + + fn reset_wait_mem_scrubbing(&self, bar: &Bar0) -> Result { + // TIMEOUT: memory scrubbing should complete in less than 10ms. + read_poll_timeout( + || Ok(regs::NV_PFALCON_FALCON_DMACTL::read(bar, &E::ID)), + |r| r.mem_scrubbing_done(), + Delta::ZERO, + Delta::from_millis(10), + ) + .map(|_| ()) + } + + fn reset_eng(&self, bar: &Bar0) -> Result { + regs::NV_PFALCON_FALCON_ENGINE::update(bar, &E::ID, |v| v.set_reset(true)); + + // TIMEOUT: falcon engine should not take more than 10us to reset. + fsleep(Delta::from_micros(10)); + + regs::NV_PFALCON_FALCON_ENGINE::update(bar, &E::ID, |v| v.set_reset(false)); + + self.reset_wait_mem_scrubbing(bar)?; + + Ok(()) + } +} diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs index b8ddfe2e5ae7..cd7b7aa6fc2a 100644 --- a/drivers/gpu/nova-core/regs.rs +++ b/drivers/gpu/nova-core/regs.rs @@ -307,6 +307,13 @@ pub(crate) fn mem_scrubbing_done(self) -> bool { 7:7 secure_stat as bool; }); +impl NV_PFALCON_FALCON_DMACTL { + /// Returns `true` if memory scrubbing is completed. + pub(crate) fn mem_scrubbing_done(self) -> bool { + !self.dmem_scrubbing() && !self.imem_scrubbing() + } +} + register!(NV_PFALCON_FALCON_DMATRFBASE @ PFalconBase[0x00000110] { 31:0 base as u32; }); @@ -389,6 +396,13 @@ pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self { // PRISCV +// RISC-V status register for debug (Turing and GA100 only). +// Reflects current RISC-V core status. +register!(NV_PRISCV_RISCV_CORE_SWITCH_RISCV_STATUS @ PFalcon2Base[0x00000240] { + 0:0 active_stat as bool, "RISC-V core active/inactive status"; +}); + +// GA102 and later register!(NV_PRISCV_RISCV_CPUCTL @ PFalcon2Base[0x00000388] { 0:0 halted as bool; 7:7 active_stat as bool; -- 2.51.0