From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C385A389116 for ; Thu, 12 Mar 2026 08:43:36 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773305018; cv=none; b=cVkaCeLeMizakaRihPKNrj2+bKLEGpxfcuDmQWgRCtySZYfD3cBeYSMRa7Ms40sa50F8FpcdG1/mSf6vOTZJV9n+cUI+hUpWZ3cLhyHAXY5EeeIzZC/tyobi/Bus91CFqhIDvmNOKWXp3E2EZeFJRAv+SIElpsRni7TnPHck7Xs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773305018; c=relaxed/simple; bh=k5SBnczWj1rqW8sWX+AhYlKbQJ8Zx8ACAwJbqctDoiU=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=qAVx8npU3WA6cH5VgBW8fdYtwn5z+rviQ/KZJV5HIyHaZAfsSLpz31+xnFTDFwVOyZXPOj/Fth7QMEWP7fH7vJzCVLqvdHpI/75Nbytv8vmapvNci40t/2Z7UFt06DDDxh9xx0MKSnQhW+FYfHw7KJHCljK0dzyIkSPgX/CxWno= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=dTJwXMLV; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="dTJwXMLV" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1773305015; bh=k5SBnczWj1rqW8sWX+AhYlKbQJ8Zx8ACAwJbqctDoiU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=dTJwXMLVXfLkC0a1MQHXmDfXWOiSdQRZGcVNcdTsfrmfefJunoUewo9Cl+SS8IjTU lGhdjvfAe6TockOlWUa8BpPeZaOXGD5s3KOLW3BDsjtyHv/tF6RitUwdlfjdkqCJx6 aKQa4RgfFmuTNHtrpFBDdZQKpbmUKmuV8P2+RR2QAmWcceC7BDA+rUJjU20Zd7zZUL DoQdI6AGW6dlsdEMIClP5NSF+kfE5azQKi1aBc0GUUNToKUfRfwxVab1mfcA298ikn 8HwLgGnbyj0tdr9H3komopHYDfqKFwbrHxvQUsBE7LTTj2pshpzCKRfz9uJtdboeoh 6vb1dtZwSglQw== Received: from fedora (unknown [IPv6:2a01:e0a:2c:6930:d919:a6e:5ea1:8a9f]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 340F217E0071; Thu, 12 Mar 2026 09:43:34 +0100 (CET) Date: Thu, 12 Mar 2026 09:43:30 +0100 From: Boris Brezillon To: Deborah Brouwer Cc: dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, Danilo Krummrich , Alice Ryhl , Daniel Almeida , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Miguel Ojeda , Gary Guo , =?UTF-8?B?QmrDtnJu?= Roy Baron , Benno Lossin , Andreas Hindborg , Trevor Gross , Steven Price , Dirk Behme , Alexandre Courbot , Boqun Feng Subject: Re: [PATCH v2 0/5] drm/tyr: Use register! macro Message-ID: <20260312094330.481ec488@fedora> In-Reply-To: <20260311-b4-tyr-use-register-macro-v2-v2-0-b936d9eb8f51@collabora.com> References: <20260311-b4-tyr-use-register-macro-v2-v2-0-b936d9eb8f51@collabora.com> Organization: Collabora X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 11 Mar 2026 16:03:57 -0700 Deborah Brouwer wrote: > This series changes the Tyr driver to use the kernel's register! macro > for hardware register access, replacing manual bit manipulation and custom > register structures with a more type-safe and maintainable approach. > > Signed-off-by: Deborah Brouwer > --- > This series depends on: > [PATCH v8 00/10] rust: add `register!` macro > https://lore.kernel.org/rust-for-linux/20260310-register-v8-0-424f80dd43bc@nvidia.com/ > > Changes in v2: > - Rebase on v8 of register! macro series; > - Add documentation; > - Remove manual functions to get address bits; > - Revise gpu_info() to use macro; > - Revise l2_power_on() to use macro; > - Set interconnect coherency protocol with macro; > - Separate commits for each register page; > - Replace HI/LO pairs with 64bit registers > - Order registers by address; > - Remove doorbell clear field from GPU_IRQ_CLEAR; > - GPU command is redesigned to accommodate multiple layouts; > - MMU register bits corrected; > - Use UPPERCASE for register names; > - Move the consts to impl block for registers; > > --- > Daniel Almeida (1): > drm/tyr: Use register! macro for GPU_CONTROL > > Deborah Brouwer (4): > drm/tyr: Set interconnect coherency during probe > drm/tyr: Use register! macro for JOB_CONTROL > drm/tyr: Use register! macro for MMU_CONTROL Could we also have a commit exposing hardware DOORBELLs as a register array? > drm/tyr: Remove custom register struct > > drivers/gpu/drm/tyr/driver.rs | 32 +- > drivers/gpu/drm/tyr/gpu.rs | 213 +++++------- > drivers/gpu/drm/tyr/regs.rs | 785 ++++++++++++++++++++++++++++++++++++------ > 3 files changed, 792 insertions(+), 238 deletions(-) > --- > base-commit: 91c02cfa16427b078c8a74f2b96123b579fdb07f > change-id: 20260311-b4-tyr-use-register-macro-v2-cdc89155045a > > Best regards,