From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from bali.collaboradmins.com (bali.collaboradmins.com [148.251.105.195]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C791E3DF00E for ; Tue, 24 Mar 2026 10:00:31 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=148.251.105.195 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774346434; cv=none; b=qXutzpXF8yStGPQidwlK41zGc2D0kuI1u9QDAm7gxbzmRjB28MaLfk6bR3xk52sdJVnDDXFeOhCIrZBGYMCgLvFGcj5PzjxHzs49Sb2rNkgUaqgYKAhE9vYDsFLd93VQXv0+vk8NIo7meVkhqujgXCRPaMxbmmV+SngQw+Yp7Y8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774346434; c=relaxed/simple; bh=XhpScIeDU+61+4GFI5u3zMrl975Ur5NFisBItgk2MpU=; h=Date:From:To:Cc:Subject:Message-ID:In-Reply-To:References: MIME-Version:Content-Type; b=fvuaP3PpX3/I+cwNAMA84iF99qaqyahpz6RZBD0AXqaeDGnkm34o0IsxRWPgl8cpql7wlc5PVN0c1RfaKSyj46w12MoF5YLwxbb3Tq5Brd9qfEaBpV/dvLn3pPg7QPbSVO4X9GGdifBfcLNKVjnC//aaR/Ecy8kxC6jYIzhe5Xg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com; spf=pass smtp.mailfrom=collabora.com; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b=lp6AkS0p; arc=none smtp.client-ip=148.251.105.195 Authentication-Results: smtp.subspace.kernel.org; dmarc=pass (p=none dis=none) header.from=collabora.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=collabora.com Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=collabora.com header.i=@collabora.com header.b="lp6AkS0p" DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=collabora.com; s=mail; t=1774346430; bh=XhpScIeDU+61+4GFI5u3zMrl975Ur5NFisBItgk2MpU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=lp6AkS0pTYkSqm+PLhnH5eLhMoNuwylOoIT+8LWBf6ewrKPdfndWlS4/5BRR5b/VE 0OXT9kjkJuFTfoXl+hdnUFczVBw4mnChkZYDxMuQfSfFxtQEk29CV3lIAng3g3pbJ5 7/Z0llRxYgoftrnoagADGMe/BJ3QDyo3wwUIth87OlohbUAjx+JRaHoNien8bIH9bf 0X1OkKhhbX9OiFdXh3a9FcbrR69yc7xEh5yEH7cvyecSEYB/EvCPujbWDD7iyOikNY d+JkrUh4JP8LNOKVDq3OVi5DFVnOQ2HqOQ16gJSiRXdZmG+1ZfKahox1H/QXFcjHaZ WboY4ayG56eYw== Received: from fedora (unknown [IPv6:2a01:e0a:2c:6930:d919:a6e:5ea1:8a9f]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (prime256v1) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) (Authenticated sender: bbrezillon) by bali.collaboradmins.com (Postfix) with ESMTPSA id 5DF2D17E4C65; Tue, 24 Mar 2026 11:00:29 +0100 (CET) Date: Tue, 24 Mar 2026 11:00:26 +0100 From: Boris Brezillon To: Deborah Brouwer Cc: dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org, Boqun Feng , Danilo Krummrich , Alice Ryhl , Daniel Almeida , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Miguel Ojeda , Gary Guo , =?UTF-8?B?QmrDtnJu?= Roy Baron , Benno Lossin , Andreas Hindborg , Trevor Gross , Steven Price , Dirk Behme , Alexandre Courbot Subject: Re: [PATCH v3 04/12] drm/tyr: Use register! macro for JOB_CONTROL Message-ID: <20260324110026.7055de82@fedora> In-Reply-To: <20260323-b4-tyr-use-register-macro-v3-v3-4-a87daf9e4701@collabora.com> References: <20260323-b4-tyr-use-register-macro-v3-v3-0-a87daf9e4701@collabora.com> <20260323-b4-tyr-use-register-macro-v3-v3-4-a87daf9e4701@collabora.com> Organization: Collabora X-Mailer: Claws Mail 4.3.1 (GTK 3.24.51; x86_64-redhat-linux-gnu) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Mon, 23 Mar 2026 17:18:06 -0700 Deborah Brouwer wrote: > Convert the JOB_CONTROL register definitions to use the `register!` macro. > > Using the `register!` macro allows us to replace manual bit masks and > shifts with typed register and field accessors, which makes the code > easier to read and avoids errors from bit manipulation. > > Co-developed-by: Daniel Almeida > Signed-off-by: Daniel Almeida > Reviewed-by: Daniel Almeida > Signed-off-by: Deborah Brouwer Reviewed-by: Boris Brezillon > --- > drivers/gpu/drm/tyr/regs.rs | 58 ++++++++++++++++++++++++++++++++++++++------- > 1 file changed, 50 insertions(+), 8 deletions(-) > > diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs > index 5ba4919263af29c6e88435099cf801fa5874b117..bae3f917dd3ad3fe0dfd8425a119347f9d1ebbe8 100644 > --- a/drivers/gpu/drm/tyr/regs.rs > +++ b/drivers/gpu/drm/tyr/regs.rs > @@ -28,7 +28,6 @@ > #![allow(dead_code)] > > use kernel::{ > - bits::bit_u32, > device::{ > Bound, > Device, // > @@ -787,14 +786,57 @@ fn from(status: McuStatus) -> Self { > } > } > > -pub(crate) const JOB_IRQ_RAWSTAT: Register<0x1000> = Register; > -pub(crate) const JOB_IRQ_CLEAR: Register<0x1004> = Register; > -pub(crate) const JOB_IRQ_MASK: Register<0x1008> = Register; > -pub(crate) const JOB_IRQ_STAT: Register<0x100c> = Register; > - > -pub(crate) const JOB_IRQ_GLOBAL_IF: u32 = bit_u32(31); > - > pub(crate) const MMU_IRQ_RAWSTAT: Register<0x2000> = Register; > pub(crate) const MMU_IRQ_CLEAR: Register<0x2004> = Register; > pub(crate) const MMU_IRQ_MASK: Register<0x2008> = Register; > pub(crate) const MMU_IRQ_STAT: Register<0x200c> = Register; > + > +/// These registers correspond to the JOB_CONTROL register page. > +/// They are involved in communication between the firmware running on the MCU and the host. > +pub(crate) mod job_control { > + use kernel::register; > + > + register! { > + /// Raw status of job interrupts. > + /// > + /// Write to this register to trigger these interrupts. > + /// Writing a 1 to a bit forces that bit on. > + pub(crate) JOB_IRQ_RAWSTAT(u32) @ 0x1000 { > + /// CSG request. These bits indicate that CSGn requires attention from the host. > + 30:0 csg; > + /// GLB request. Indicates that the GLB interface requires attention from the host. > + 31:31 glb; Should this be 31:31 glb => bool; ? > + } > + > + /// Clear job interrupts. Write only. > + /// > + /// Write a 1 to a bit to clear the corresponding bit in [`JOB_IRQ_RAWSTAT`]. > + pub(crate) JOB_IRQ_CLEAR(u32) @ 0x1004 { > + /// Clear CSG request interrupts. > + 30:0 csg; > + /// Clear GLB request interrupt. > + 31:31 glb; > + } > + > + /// Mask for job interrupts. > + /// > + /// Set each bit to 1 to enable the corresponding interrupt source or to 0 to disable it. > + pub(crate) JOB_IRQ_MASK(u32) @ 0x1008 { > + /// Enable CSG request interrupts. > + 30:0 csg; > + /// Enable GLB request interrupt. > + 31:31 glb; > + } > + > + /// Active job interrupts. Read only. > + /// > + /// This register contains the result of ANDing together [`JOB_IRQ_RAWSTAT`] and > + /// [`JOB_IRQ_MASK`]. > + pub(crate) JOB_IRQ_STATUS(u32) @ 0x100c { > + /// CSG request interrupt status. > + 30:0 csg; > + /// GLB request interrupt status. > + 31:31 glb; > + } > + } > +} >