Re: [PATCH v3 09/12] drm/tyr: Add fields for COMMAND register

[Boris Brezillon <boris.brezillon@collabora.com>]

On Mon, 23 Mar 2026 17:18:11 -0700
Deborah Brouwer <deborah.brouwer@collabora.com> wrote:

> The MMU COMMAND register accepts specific commands. Enumerate those
> commands and use the register! macro to ensure that only those commands
> can be written to the MMU COMMAND register.
> 
> Signed-off-by: Deborah Brouwer <deborah.brouwer@collabora.com>

Reviewed-by: Boris Brezillon <boris.brezillon@collabora.com>

Though I'm wondering why we do that in multiple steps. I'd rather have
a single commit defining everything MMU related (basically patches 5 and
7-11 merged into a single commit).

> ---
>  drivers/gpu/drm/tyr/regs.rs | 47 ++++++++++++++++++++++++++++++++++++++++++++-
>  1 file changed, 46 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/tyr/regs.rs b/drivers/gpu/drm/tyr/regs.rs
> index 9bf2723ab6412034be9a77930532cc89d0adb128..6fbd6268724eb6b2ea8d76c5d991353dcbe87068 100644
> --- a/drivers/gpu/drm/tyr/regs.rs
> +++ b/drivers/gpu/drm/tyr/regs.rs
> @@ -1048,8 +1048,53 @@ fn from(val: MMU_MEMATTR_STAGE1) -> Self {
>                  63:12   base;
>              }
>  

nit: do we need an extra blank line here?

> +        }
> +
> +        /// Helpers for MMU COMMAND register.
> +        #[derive(Copy, Clone, Debug)]
> +        #[repr(u8)]
> +        pub(crate) enum MmuCommand {
> +            /// No operation, nothing happens.
> +            Nop = 0,
> +            /// Propagate settings to the MMU.
> +            Update = 1,
> +            /// Lock an address region.
> +            Lock = 2,
> +            /// Unlock an address region.
> +            Unlock = 3,
> +            /// Clean and invalidate the L2 cache, then unlock.
> +            FlushPt = 4,
> +            /// Clean and invalidate all caches, then unlock.
> +            FlushMem = 5,
> +        }
> +
> +        impl TryFrom<Bounded<u32, 8>> for MmuCommand {
> +            type Error = Error;
> +
> +            fn try_from(val: Bounded<u32, 8>) -> Result<Self, Self::Error> {
> +                match val.get() {
> +                    0 => Ok(MmuCommand::Nop),
> +                    1 => Ok(MmuCommand::Update),
> +                    2 => Ok(MmuCommand::Lock),
> +                    3 => Ok(MmuCommand::Unlock),
> +                    4 => Ok(MmuCommand::FlushPt),
> +                    5 => Ok(MmuCommand::FlushMem),
> +                    _ => Err(EINVAL),
> +                }
> +            }
> +        }
> +
> +        impl From<MmuCommand> for Bounded<u32, 8> {
> +            fn from(cmd: MmuCommand) -> Self {
> +                (cmd as u8).into()
> +            }
> +        }
> +
> +        register! {
>              /// MMU command register for each address space. Write only.
> -            pub(crate) COMMAND(u32)[MAX_AS, stride = STRIDE] @ 0x2418 {}
> +            pub(crate) COMMAND(u32)[MAX_AS, stride = STRIDE] @ 0x2418 {
> +                7:0     command ?=> MmuCommand;
> +            }
>  
>              /// Fault status register for each address space. Read only.
>              pub(crate) FAULTSTATUS(u32)[MAX_AS, stride = STRIDE] @ 0x241c {}
>