Re: [PATCH v3 01/12] drm/tyr: Use register! macro for GPU_CONTROL

[Boris Brezillon <boris.brezillon@collabora.com>]

On Tue, 24 Mar 2026 12:23:54 +0100
"Danilo Krummrich" <dakr@kernel.org> wrote:

> On Tue Mar 24, 2026 at 1:18 AM CET, Deborah Brouwer wrote:
> > +    register! {
> > +        /// GPU identification register.
> > +        pub(crate) GPU_ID(u32) @ 0x0 {
> > +            /// Status of the GPU release.
> > +            3:0     ver_status;
> > +            /// Minor release version number.
> > +            11:4    ver_minor;
> > +            /// Major release version number.
> > +            15:12   ver_major;
> > +            /// Product identifier.
> > +            19:16   prod_major;
> > +            /// Architecture patch revision.
> > +            23:20   arch_rev;
> > +            /// Architecture minor revision.
> > +            27:24   arch_minor;
> > +            /// Architecture major revision.
> > +            31:28   arch_major;
> > +        }  
> 
> Are you sure that this is the field order you want to choose for Tyr? nova-core
> had this order in the past (we're changing this currently), as it came from
> OpenRM headers, but it is pretty unusual for datasheets and TRMs, which is also
> why the register!() macro examples use the typical and recommended order, i.e.
> 
> 	pub(crate) GPU_ID(u32) @ 0x0 {
> 	    /// Architecture major revision.
> 	    31:28   arch_major;
> 	    /// Architecture minor revision.
> 	    27:24   arch_minor;
> 	    /// Architecture patch revision.
> 	    23:20   arch_rev;
> 	    /// Product identifier.
> 	    19:16   prod_major;
> 	    /// Major release version number.
> 	    15:12   ver_major;
> 	    /// Minor release version number.
> 	    11:4    ver_minor;
> 	    /// Status of the GPU release.
> 	    3:0     ver_status;
> 	}

It's defined in ascending bit order in the datasheets we have, so if
we're ever going to auto-generate those from the xml, we'd likely have
the same definitions Deborah came up with, unless the script re-orders
things in descending bit order.