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Tue, 14 Jul 2026 09:58:29 -0700 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v4 0/1] Rust PCI capability infrastructure and SR-IOV support Date: Tue, 14 Jul 2026 19:58:25 +0300 Message-ID: <20260714165827.2937960-1-zhiw@nvidia.com> X-Mailer: git-send-email 2.51.0 Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF00001506:EE_|SJ0PR12MB5664:EE_ X-MS-Office365-Filtering-Correlation-Id: 0e6a7e4a-1728-4733-2017-08dee1c92ec6 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|376014|1800799024|7416014|23010399003|82310400026|6133799003|5023799004|11063799006|56012099006|18002099003|13003099007; X-Microsoft-Antispam-Message-Info: k1gkMn1MyQhdqfqCOl8D2AzEwXJ52apNKAybgq6LKkrHXh+ovRotiIm6+FzXJJHoy4Ga0QmQpuk4ImckVmBWvSnG97X4pROUrXIC9tVVSKFSz4PcEuz7eYnJ6U1CKoTijEDzG5F6V2iMlJ8hNhXw+89i4u1gR6wQSDQc9mBtnJQO96e7N7WXMA/Sn8Iku+60MOEumDXKqsFTydqPJ9eAalHw0EKwja3MI0vTIf2vhSt+vkt85ue4FLj2bAxbYxiYzrHXcwSTukeGwZU3msOEW1CvQfggGa2xBD57iilXRrIZFOir3vvPgD6hh2O0NTPmABLxUsfe5mxGS2DzQhFX9Z+sLcS6z0CXNCfIUQQSS0TDHAxvLMnZdS8gukZglIEmjRozhUrxnTxJfrKKHbVLcRn9XpVyD064uXS1w+wPVWRsWk4PfRIcDNdkL1Yu1yS/mf1etLCegQjbwA+WswR8o+/0aOyVhNLRf0YEPHhccD4/NELsauGSKi9kXVXRo2Tve7oVU/OPbmx0rD9e7ws2SXOShRPuGs6JVzhl3Qkos2cdekrJ+7dEqOms+HXnjmWxUand8SsM6v0cC8ZnnpvSLyreBB4uWgDrX5nOKlTcytFdgb6CH/wWZTl8tWmiUxnaLBphCuLFy17BvrZB4921BHsZffwJCT4mvWtMJXbA3okclqK1IlJrrJULLKoH+JKGf5xKMLR2mB3s6a+wSa2maw== X-Forefront-Antispam-Report: CIP:216.228.118.232;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc7edge1.nvidia.com;CAT:NONE;SFS:(13230040)(36860700016)(376014)(1800799024)(7416014)(23010399003)(82310400026)(6133799003)(5023799004)(11063799006)(56012099006)(18002099003)(13003099007);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: CHLFn27eyt5AlsYP235xk0i64U3FT/3/o+BSB6rDMR5DYHE76gWN/NGYk4/Uqi4fo2jwO4yJwo5azhR2Or4X/mY+SoYKPfrr7jipDAfIzrv27bhTti1N12RQKzt1JvNMha7ZNU4AZNp4TarODQcfE1+EMOIsrfi1A/6cpvY+b2YyDFy7Y473S7ysBjWHU0vHRQXNXz5/71RXRen0uinkB/iof2kxHltZXfUBrdrCXYDmpmi1kzI9blHTFVwghwKz1a+Xn0EqK0ePjf1cyayqtyzxW2Y6b91IaF5GiArGNfqvKJeJk/DsDgwIpvmWzgU9vNOl/AWt78EMPKzgNhO69tNkEoDzgA5lYQkeJW8ZgMzmZ4r8XJ3iqcVeXqwnwbJ0BJG/BnBoEtMhhDFRZuaygCslyj0vsFJtMruFbFqJcUdwLehFv67a1qVaa/DMZQSX X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 14 Jul 2026 16:58:52.1319 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 0e6a7e4a-1728-4733-2017-08dee1c92ec6 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.232];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF00001506.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB5664 This is a follow-up to v3 [1], reworked to address Alexandre Courbot's review [2] and the VF BAR API follow-up [3]. This version is based on the latest driver-core-next. This patch has been used in the Boot GSP with vGPU enabled series [6]. For context, v3 was a follow-up to the RFC v2 series [4], reworked on top of Gary's io_projection patches [5]. The patch defines an ExtCapability trait that associates an extended capability ID with its register layout. The generic ConfigSpace::find_ext_capability() finder locates the capability, bounds it at the next capability or the end of extended configuration space, and projects the ConfigSpace view to the requested layout. This lets the existing I/O projection and access macros operate on capability registers. ExtSriovRegs provides the SR-IOV register layout, with helpers to identify and read 64-bit VF BARs. ExtSriovCapability remains as a convenience alias. Changes since v3: - Replaced the custom ExtCapability I/O wrapper with the existing ConfigSpace view infrastructure. (Alex) - Reused ExtCapability as a trait carrying the capability ID, and made ConfigSpace::find_ext_capability() generic over register layouts. (Alex) - Removed public cast_sized() and unused find_next_ext_capability(). (Alex) - Kept capability construction in the generic finder and documented calculate_ext_cap_size(). (Alex) - Used PCI_SRIOV_NUM_BARS rather than a literal VF BAR count. (Alex, Zhi) - Added is_vf_bar_64bit() and made read_vf_bar64() reject BARs that are not 64-bit memory BARs. (Alex, Zhi) - Kept indexed VF BAR helpers because the Nova user accesses fixed BAR slots rather than iterating over them. (Alex) - Adapted the implementation and doctest to the current ConfigSpace I/O APIs. (Zhi) Changes since RFC v2: - Hardened calculate_ext_cap_size() against corrupt capability lists. (Zhi) - Added // INVARIANT: comments at all ExtCapability construction sites (make_ext_capability and cast_sized). (Zhi) - Added #[inline] to small forwarding methods (find, read_vf_bar64). (Zhi) Changes since RFC: - Rebased on io_projection branch, using Gary's Io/IoCapable traits. (Gary) - ExtCapability implements Io and delegates IoCapable to ConfigSpace instead of duplicating config read/write logic. (Gary) - Dropped the fallible I/O patch (now upstream in this tree). (Zhi) - Added Rust helper for PCI_EXT_CAP_NEXT() macro. (Zhi) - Replaced raw `as` casts with From conversions where possible. (Zhi) - Renamed SriovRegs/SriovCapability to ExtSriovRegs/ExtSriovCapability. (Zhi) [1] https://lore.kernel.org/rust-for-linux/20260409185254.3869808-1-zhiw@nvidia.com/ [2] https://lore.kernel.org/rust-for-linux/DHRTUAF52GNI.1J98TSAG1LS6Q@nvidia.com/ [3] https://lore.kernel.org/rust-for-linux/DI2SL4G5INLY.2W1IFTR081ID3@nvidia.com/ [4] https://lore.kernel.org/rust-for-linux/20260225180449.1813833-1-zhiw@nvidia.com/ [5] https://lore.kernel.org/rust-for-linux/20260323153807.1360705-1-gary@kernel.org/ [6] https://lore.kernel.org/rust-for-linux/20260313165336.935771-1-zhiw@nvidia.com/ Zhi Wang (1): rust: pci: add extended capability and SR-IOV support rust/helpers/pci.c | 5 + rust/kernel/pci.rs | 7 ++ rust/kernel/pci/cap.rs | 209 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 221 insertions(+) create mode 100644 rust/kernel/pci/cap.rs base-commit: b07fc8d60bd30caaba4d293929459780166da194 -- 2.51.0