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Thu, 30 Jul 2026 11:29:56 -0700 From: Zhi Wang To: , , CC: , , , , , , , , , , , , , , , , , , , , , , , , "Zhi Wang" Subject: [PATCH v6 0/1] Rust PCI capability infrastructure and SR-IOV support Date: Thu, 30 Jul 2026 21:29:52 +0300 Message-ID: <20260730182954.783568-1-zhiw@nvidia.com> X-Mailer: git-send-email 2.53.0 Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL6PEPF0001AB4C:EE_|SA5PPF590085732:EE_ X-MS-Office365-Filtering-Correlation-Id: 92522b4c-cc51-4a49-0d3d-08deee689ffe X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|36860700016|82310400026|1800799024|376014|7416014|56012099006|13003099007|10067099003|18002099003|6133799003|11063799006|5023799004; X-Microsoft-Antispam-Message-Info: gVMsBnTbS/Nq3heGeC2stUfraebhcBh0iM26rsjU8U23GpQ6TN4oRWfcC2TqfN9uw6/8BgfXDPrMd0zdQqd/T3Gm4EtwEZ2ButC652+gX4ZR9pq2gerbzIIev76JU1FJk3nMQTu26ZaYPmzCwHzhUVLf694Vn+kfn+nV+cGQhpuAc1iyXMuQg9wFD6bEvVTnBdgVcxkzB6Jvbp/3XSeGmQ7yE08gjCIHhXcr8C9s9eFVggwbMB5xuwfyZZdvkI08fm88LeF07wKLYMbW15ENu4dKg3dZgAKVnf8Sc0vYuAEnFDsxX8EpOI9g16hmuzG+V52j66swO6nIFutate9AH9RUnUF7QbZMiivo9RSt3P3dB5REIWqg4wMlPmHxoml6dBa3MZBy9ErbOT8ASrJwE+YhxWRP15dNeOGTKkHV1fLOi0/QJfjBReqqrSOXb1IGC0oNxkiYxtKMNhDXw7Wtg836Hg1PJ/wp/6olgaQBQWBK+C2xRhZvyAeQm+yS9QELL+d4J0XKlwqclvs4Nbt7wV7qF9zGDh6AKyLFfPWkY9XmXQydxL/uPvX5yV67ALby14+9xKijHiOQpUNSA6sOhd0Fs46oVwdzfNWZAaooQTplXkuowGT7/5/zSc8nwAJfGyS9jZaJJoptsL0gMfAG/oLCRTLqMPrvNAbX/w0K7mt1X/ycleaRJuiO8wQ8jRKQ41BYQblq5DEWxByxrH8mkg== X-Forefront-Antispam-Report: CIP:216.228.117.161;CTRY:US;LANG:en;SCL:1;SRV:;IPV:NLI;SFV:NSPM;H:mail.nvidia.com;PTR:dc6edge2.nvidia.com;CAT:NONE;SFS:(13230040)(23010399003)(36860700016)(82310400026)(1800799024)(376014)(7416014)(56012099006)(13003099007)(10067099003)(18002099003)(6133799003)(11063799006)(5023799004);DIR:OUT;SFP:1101; X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: g7CxYiun9ktagf5S0T1t/LGmu9ZF5T/wW3xZEB8jdHpnwLhTNyMGW2BgJV99cpzgY4uqrWl4AJohBfD0xw4HM8FOkP942DvwiRliehdRCHxkpYUY+yaaS0l/4Nd4wVerK5vuiWOIT9R3x1m+HaNA0S/HmRO8TuekzY9tHptnNB8pzJfMknDl8b6Flik6Tf/7qPdtk2mYhy4hcHhnpG0nNPeQ6yWSEEphLH1QYuRpF2tHymZIhi1WXrj6AqTSZj3dthTASgw4k18/+m6gLZrRj+IruAPIU2Xi9sH1FNH2kYEFrNV8J0k9d8Xc6eY7uP+Vs6RWZNuEE0IISEfDzOpe5JhZ7x55FoZ1guriF+pXrFdK6Nq8qu8jsCdWV66xyWClQNRg4pGA/QFSHsw1QMIPBE6Zl3Uf1V9mzjBgjfFA/z3Bf7mFae72n5T0/6LyP9A5 X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Jul 2026 18:30:25.9512 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 92522b4c-cc51-4a49-0d3d-08deee689ffe X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL6PEPF0001AB4C.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA5PPF590085732 This is a follow-up to v5 [8], reworked to address the Sashiko review [9]. This version is based on drm-rust-next. This patch has been used in the Boot GSP with vGPU enabled series [6]. The patch defines an ExtCapability trait that associates an extended capability ID with its register layout. The generic ConfigSpace::find_ext_capability() finder locates the capability, bounds it at the next capability or the end of extended configuration space, and projects the ConfigSpace view to the requested layout. This lets the existing I/O projection and access macros operate on capability registers. ExtSriovRegs provides the SR-IOV register layout. ConfigSpace::read_vf_bar() decodes a VF memory BAR into ExtSriovVfBar, which exposes its address and 64-bit status, plus the configuration-space slot of the next logical BAR. ExtSriovCapability remains as a convenience alias. Changes since v5: - Removed the unused ConfigSpace> offset() and size() inherent methods; ConfigSpace already provides size through the Io trait. (Sashiko, Zhi) - Removed the doctest write to the SR-IOV NumVFs register, avoiding an example that bypasses PCI core SR-IOV state management. (Sashiko) - Corrected Function Dependency Link to an 8-bit field followed by its reserved byte, matching the PCIe SR-IOV register layout. (Sashiko) Changes since v4: - Replaced the separate is_vf_bar_64bit() and read_vf_bar64() helpers with read_vf_bar(), returning a decoded ExtSriovVfBar. (Zhi) - Moved memory BAR attribute stripping into the PCI abstraction and used named PCI attribute definitions rather than an open-coded mask. (Zhi) - Exposed the next logical BAR slot so callers can walk mixed 32-bit and 64-bit VF BAR layouts without duplicating slot arithmetic. (Zhi) - Updated the doctest and PCI exports for the decoded BAR API. (Zhi) Changes since v3: - Replaced the custom ExtCapability I/O wrapper with the existing ConfigSpace view infrastructure. (Alex) - Reused ExtCapability as a trait carrying the capability ID, and made ConfigSpace::find_ext_capability() generic over register layouts. (Alex) - Removed public cast_sized() and unused find_next_ext_capability(). (Alex) - Kept capability construction in the generic finder and documented calculate_ext_cap_size(). (Alex) - Used PCI_SRIOV_NUM_BARS rather than a literal VF BAR count. (Alex, Zhi) - Added is_vf_bar_64bit() and made read_vf_bar64() reject BARs that are not 64-bit memory BARs. (Alex, Zhi) - Kept indexed VF BAR helpers because the Nova user accesses fixed BAR slots rather than iterating over them. (Alex) - Adapted the implementation and doctest to the current ConfigSpace I/O APIs. (Zhi) Changes since RFC v2: - Hardened calculate_ext_cap_size() against corrupt capability lists. (Zhi) - Added // INVARIANT: comments at all ExtCapability construction sites (make_ext_capability and cast_sized). (Zhi) - Added #[inline] to small forwarding methods (find, read_vf_bar64). (Zhi) Changes since RFC: - Rebased on io_projection branch, using Gary's Io/IoCapable traits. (Gary) - ExtCapability implements Io and delegates IoCapable to ConfigSpace instead of duplicating config read/write logic. (Gary) - Dropped the fallible I/O patch (now upstream in this tree). (Zhi) - Added Rust helper for PCI_EXT_CAP_NEXT() macro. (Zhi) - Replaced raw `as` casts with From conversions where possible. (Zhi) - Renamed SriovRegs/SriovCapability to ExtSriovRegs/ExtSriovCapability. (Zhi) [1] https://lore.kernel.org/rust-for-linux/20260409185254.3869808-1-zhiw@nvidia.com/ [2] https://lore.kernel.org/rust-for-linux/DHRTUAF52GNI.1J98TSAG1LS6Q@nvidia.com/ [3] https://lore.kernel.org/rust-for-linux/DI2SL4G5INLY.2W1IFTR081ID3@nvidia.com/ [4] https://lore.kernel.org/rust-for-linux/20260225180449.1813833-1-zhiw@nvidia.com/ [5] https://lore.kernel.org/rust-for-linux/20260323153807.1360705-1-gary@kernel.org/ [6] https://lore.kernel.org/rust-for-linux/20260313165336.935771-1-zhiw@nvidia.com/ [7] https://lore.kernel.org/rust-for-linux/20260714165827.2937960-1-zhiw@nvidia.com/ [8] https://lore.kernel.org/rust-for-linux/20260730180349.771719-1-zhiw@nvidia.com/ [9] https://sashiko.dev/#/patchset/20260730180349.771719-2-zhiw@nvidia.com?part=1 Zhi Wang (1): rust: pci: add extended capability and SR-IOV support rust/helpers/pci.c | 5 + rust/kernel/pci.rs | 8 ++ rust/kernel/pci/cap.rs | 236 +++++++++++++++++++++++++++++++++++++++++ 3 files changed, 249 insertions(+) create mode 100644 rust/kernel/pci/cap.rs base-commit: 93b9511a3bba7f31d95502e5f912f0a476b0cf4a -- 2.53.0