Re: [PATCH 16/31] gpu: nova-core: Hopper/Blackwell: add FSP message infrastructure

[Joel Fernandes <joelagnelf@nvidia.com>]

On 12/3/2025 12:59 AM, John Hubbard wrote:
> Add the FSP messaging infrastructure needed for Chain of Trust
> communication on Hopper/Blackwell GPUs.
> 
> Signed-off-by: John Hubbard <jhubbard@nvidia.com>
> ---
>  drivers/gpu/nova-core/falcon/fsp.rs | 77 +++++++++++++++++++++++++++++
>  drivers/gpu/nova-core/regs.rs       | 48 ++++++++++++++++++
>  2 files changed, 125 insertions(+)
> 
> diff --git a/drivers/gpu/nova-core/falcon/fsp.rs b/drivers/gpu/nova-core/falcon/fsp.rs
> index 9e796e82e556..0e8522b1171d 100644
> --- a/drivers/gpu/nova-core/falcon/fsp.rs
> +++ b/drivers/gpu/nova-core/falcon/fsp.rs
> @@ -87,4 +87,81 @@ pub(crate) fn read_emem(&self, bar: &Bar0, offset: u32, data: &mut [u8]) -> Resu
>  
>          Ok(())
>      }
> +
> +    /// Poll FSP for incoming data.
> +    ///
> +    /// Returns the size of available data in bytes, or 0 if no data is available.
> +    ///
> +    /// The FSP message queue is not circular - pointers are reset to 0 after each
> +    /// message exchange, so `tail >= head` is always true when data is present.
> +    #[allow(dead_code)]
> +    pub(crate) fn poll_msgq(&self, bar: &Bar0) -> u32 {
> +        let head = regs::NV_PFSP_MSGQ_HEAD::read(bar).address();
> +        let tail = regs::NV_PFSP_MSGQ_TAIL::read(bar).address();
> +
> +        if head == tail {
> +            return 0;
> +        }
> +
> +        // TAIL points at last DWORD written, so add 4 to get total size
> +        (tail - head) + 4
> +    }
> +

Can we harden against integer underflow here? Even if tail is always >= head in
normal operation, I think we should prepare for underflow due to misbehaving HW
etc to avoid producing a massive integer, how about:

    tail.saturating_sub(head) + 4

Thanks.