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Tue, 10 Sep 2024 15:10:41 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 10 Sep 2024 20:10:21 +0100 From: "Jiaxun Yang" To: "Maciej W. Rozycki" Cc: "Masahiro Yamada" , "Nathan Chancellor" , "Nicolas Schier" , "Richard Weinberger" , "Anton Ivanov" , "Johannes Berg" , "Thomas Gleixner" , "Ingo Molnar" , "Borislav Petkov" , "Dave Hansen" , x86@kernel.org, "H. Peter Anvin" , "Miguel Ojeda" , "Alex Gaynor" , "Wedson Almeida Filho" , "Boqun Feng" , "Gary Guo" , =?UTF-8?Q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Thomas Bogendoerfer" , "Steven Rostedt" , "Masami Hiramatsu" , "Mark Rutland" , "Jonathan Corbet" , "Alex Shi" , "Yanteng Si" , "Nick Desaulniers" , "Bill Wendling" , "Justin Stitt" , linux-kbuild@vger.kernel.org, linux-kernel@vger.kernel.org, linux-um@lists.infradead.org, rust-for-linux@vger.kernel.org, "linux-mips@vger.kernel.org" , linux-trace-kernel@vger.kernel.org, linux-doc@vger.kernel.org, llvm@lists.linux.dev Message-Id: <54ce7574-43fd-40ee-9ae9-dd72283d1040@app.fastmail.com> In-Reply-To: References: <20240905-mips-rust-v2-0-409d66819418@flygoat.com> <20240905-mips-rust-v2-3-409d66819418@flygoat.com> <035ccfe5-c368-4cd9-8e0d-34e0e355cb05@app.fastmail.com> Subject: Re: [PATCH v2 3/3] rust: Enable for MIPS Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable =E5=9C=A82024=E5=B9=B49=E6=9C=8810=E6=97=A5=E4=B9=9D=E6=9C=88 =E4=B8=8B=E5= =8D=885:03=EF=BC=8CMaciej W. Rozycki=E5=86=99=E9=81=93=EF=BC=9A > On Mon, 9 Sep 2024, Jiaxun Yang wrote: > >> > What's the consequence of using `mips2' rather than `mips1' here? = How=20 >> > about other ISA revisions, e.g. `mips4' (that also applies to the 6= 4BIT=20 >> > leg)? >>=20 >> LLVM's mips1 backend is a little bit broken beyond repair, so I tried= to use mips2 >> as a baseline. I should probably let HAVE_RUST depend on !CPU_R3000 t= o get it covered. > > GCC works just fine I suppose, just as with the other language fronte= nds,=20 > doesn't it? Nah, currently we can only use rustc with LLVM backend. target.json file we are generating here is also LLVM backend only for rustc. gccrs is not usable for kernel yet. > >> We have no good way to tell ISA reversion prior to R1 just from Kconf= ig TARGET_ISA_REV, >> valid numbers for TARGET_ISA_REV are only 1, 2, 5, 6 from Kconfig. > > This approach doesn't work for some MIPS architecture processor confi= gs=20 > anyway, e.g. what ISA revision will CPU_P5600 imply here? TARGET_ISA_REV will be set to 5 for CPU_P5600 (CPU_MIPSR5 will default t= o y on CPU_P5600, and CPU_MIPSR5 sets TARGET_ISA_REV to 5).=20 > > However if there's a need (and previously there wasn't), then I think= it=20 > can be sorted in a straightforward way. We have just a bunch of CPU_*=20 > settings and we can define corresponding ISA_* settings to select, e.g= .=20 > ISA_MIPS1, ISA_MIPS3, ISA_MIPS32_R1, ISA_MIPS64_R6, and so on, based o= n=20 > information extracted from per-CPU_* `-march=3D' compilation flags fro= m=20 > arch/mips/Makefile (possibly combined with ISA data obtained from=20 > GCC/binutils for said flags). > > It could be a bit tedious to write, but not a big challenge really, j= ust=20 > mechanical work. TARGET_ISA_REV is guaranteed to be aligned with CPU's supported ISA for = now, so I see no reason to invent another set of symbols.... > >> Given that mips 2 and 3 binaries (Rust object files) can link run fla= wlessly on all pre-R6 >> (despite R3000) hardware with matching bitness, they were chosen as f= allback here. > > I'm fine with having a MIPS1/R3000 exception for broken LLVM, but I s= ee=20 > no reason to disable it for GCC. It actually reminds me that LLVM lacks R4000 and some other workarounds = as well. I shall fix those in Kconfig as well. Thanks > > Maciej --=20 - Jiaxun