From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A295F2D321A; Thu, 9 Oct 2025 12:54:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760014456; cv=none; b=F7HMpHROvPwD37p9lGTIdU0p5lH0NvpSzGsrXvzSy7CnByYarBl5nF7KZDoWr1MyuDSKostxKX1P3hM2lqoWsnXnGyRh/d9FpDDhreBzJ9JnWOl3mpYmdDnt23Oi9ZGZz6jJMoEl/yrAzAH9A+yemz4pWQYUeX2SDaUYa0a0zx8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1760014456; c=relaxed/simple; bh=R1TORzTxYknOCobqa5N2Ym/eV3oIkS/TL69ydYBPELo=; h=Message-ID:Date:MIME-Version:Subject:To:Cc:References:From: In-Reply-To:Content-Type; b=du6tMM+iD1HkC7wnDozUezIDlc0FnLRN5AQVz2eOGJe5zZ2bXrWKJMBGJb0ctJLjDGrKnl4nvbWBOGFMzFPqmooiRDhpr1ooUIY3r+Tf6MTuydnBEmcW44JTVHEhBX/sDKPgeds5nMNXPO2yVaVJj99NPH6ClrCW10asfxVf4VA= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ZHOtDTn5; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ZHOtDTn5" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E4AF2C4CEE7; Thu, 9 Oct 2025 12:54:10 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1760014456; bh=R1TORzTxYknOCobqa5N2Ym/eV3oIkS/TL69ydYBPELo=; h=Date:Subject:To:Cc:References:From:In-Reply-To:From; b=ZHOtDTn5E5ki97MoLFbg/hqT6PHek9RAtK++CrFn/XyiyBMbFi4k1QwsKrqf6cJKG 4NQyQB7rM4j5LUn3I7Ys3/kuTjEPoWBu9aTR/zvv9riMPS3x2YvltdyvnRqojfieOK w6Kd53MaLy02LrSMe/3oprCkG0+IX+Q6aGG8DWk+loOmJOi8ohYdfRorqkbx0BRAlc NxskVlGcPMtrsq1gKH6OV7Nu4UCO2YYDRSG/SPJ2VZJvOr3qSttg6EqXMSJ0OLAXCa V7Kw4G3OmpyPjie7YjAsSnCTxT9lQ7jK8k4ro7YPK2UIU4IuSQ3I1CTkdWLzScVUNX hKULQMpCJMzGA== Message-ID: <807fe91b-acc6-4faf-834c-ced0dead2605@kernel.org> Date: Thu, 9 Oct 2025 14:54:09 +0200 Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v6 4/5] rust: Move register and bitfield macros out of Nova To: Alexandre Courbot Cc: Dirk Behme , Joel Fernandes , linux-kernel@vger.kernel.org, rust-for-linux@vger.kernel.org, dri-devel@lists.freedesktop.org, Alistair Popple , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , bjorn3_gh@protonmail.com, Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , David Airlie , Simona Vetter , Maarten Lankhorst , Maxime Ripard , Thomas Zimmermann , John Hubbard , Timur Tabi , joel@joelfernandes.org, Elle Rhumsaa , Yury Norov , Daniel Almeida , Andrea Righi , nouveau@lists.freedesktop.org References: <20251003154748.1687160-1-joelagnelf@nvidia.com> <20251003154748.1687160-5-joelagnelf@nvidia.com> <5a5bd549-f5b7-41ec-b493-bda427d1218f@de.bosch.com> From: Danilo Krummrich Content-Language: en-US In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit On 10/9/25 1:28 PM, Alexandre Courbot wrote: > On Thu Oct 9, 2025 at 8:16 PM JST, Danilo Krummrich wrote: >> On Thu Oct 9, 2025 at 8:59 AM CEST, Dirk Behme wrote: >>> Assuming that register.rs is supposed to become the "generic" way to >>> access hardware registers I started to have a look to it. Some weeks >>> back testing interrupts I used some quite simple timer with 4 registers >>> [1]. Now, thinking about converting it to register!() I have three >>> understanding / usage questions: >>> >>> * At the moment register!() is for 32-bit registers, only? So it can't >>> be used for my example having 8-bit and 16-bit registers as well? >> >> Yes, currently the register!() macro always generates a 32-bit register type >> (mainly because nova-core did not need anything else). However, this will of >> course be generalized (which should be pretty straight forward). >> >> Having a brief look at the TMU datasheet it looks like you should be able to >> treat TSTR and TCR as 32-bit registers without any issues for testing the >> register!() macro today. I.e. you can just define it as: >> >> register!(TSTR @ 0x04, "Timer Start Register" { >> 2:2 str2 as bool, "Specifies whether TCNT2 is operated or stopped."; >> 1:1 str1 as bool, "Specifies whether TCNT1 is operated or stopped."; >> 0:0 str0 as bool, "Specifies whether TCNT0 is operated or stopped."; >> }); >> >> Same for TCR. > > Patch 2 of this series actually adds support for 16 and 8 bit register > storage. Heh! I knew I saw a patch for this already somewhere, seems like I missed the forest for the trees. :)