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charset=UTF-8 Date: Tue, 03 Jun 2025 17:03:02 +0900 Message-Id: Cc: "John Hubbard" , "Ben Skeggs" , "Joel Fernandes" , "Timur Tabi" , "Alistair Popple" , , , , Subject: Re: [PATCH v4 14/20] gpu: nova-core: add falcon register definitions and base code From: "Alexandre Courbot" To: "Lyude Paul" , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "Danilo Krummrich" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" X-Mailer: aerc 0.20.1-0-g2ecb8770224a References: <20250521-nova-frts-v4-0-05dfd4f39479@nvidia.com> <20250521-nova-frts-v4-14-05dfd4f39479@nvidia.com> In-Reply-To: X-ClientProxiedBy: TYCP286CA0172.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3c6::10) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DM4PR12MB6109:EE_ X-MS-Office365-Filtering-Correlation-Id: 3cc536f9-a45d-44e7-6575-08dda27511df X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|10070799003|7416014|376014|921020; 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On Sat May 31, 2025 at 7:22 AM JST, Lyude Paul wrote: >> + /// `target_mem`. >> + /// >> + /// `sec` is set if the loaded firmware is expected to run in secur= e mode. >> + fn dma_wr( >> + &self, >> + bar: &Bar0, >> + dma_handle: bindings::dma_addr_t, >> + target_mem: FalconMem, >> + load_offsets: FalconLoadTarget, >> + sec: bool, >> + ) -> Result { >> + const DMA_LEN: u32 =3D 256; >> + >> + // For IMEM, we want to use the start offset as a virtual addre= ss tag for each page, since >> + // code addresses in the firmware (and the boot vector) are vir= tual. >> + // >> + // For DMEM we can fold the start offset into the DMA handle. >> + let (src_start, dma_start) =3D match target_mem { >> + FalconMem::Imem =3D> (load_offsets.src_start, dma_handle), >> + FalconMem::Dmem =3D> ( >> + 0, >> + dma_handle + load_offsets.src_start as bindings::dma_ad= dr_t, > > I wonder if maybe we shouldn't use dma_addr_t directly from bindings and = add a > proper type alias for it somewhere? I guess so, let me see if I can easily change CoherentAllocation to support that (and address Danilo's related comment). >> +pub(crate) trait FalconHal: Sync { >> + // Activates the Falcon core if the engine is a risvc/falcon dual e= ngine. >> + fn select_core(&self, _falcon: &Falcon, _bar: &Bar0) -> Result<(= )> { > > Could just be Result > >> + Ok(()) >> + } >> + >> + /// Returns the fused version of the signature to use in order to r= un a HS firmware on this >> + /// falcon instance. `engine_id_mask` and `ucode_id` are obtained f= rom the firmware header. >> + fn get_signature_reg_fuse_version( >> + &self, >> + falcon: &Falcon, >> + bar: &Bar0, >> + engine_id_mask: u16, >> + ucode_id: u8, >> + ) -> Result; >> + >> + // Program the boot ROM registers prior to starting a secure firmwa= re. >> + fn program_brom(&self, falcon: &Falcon, bar: &Bar0, params: &Fal= conBromParams) >> + -> Result<()>; > > Same here Urrk I've done this throughout the code. Fixed them all, thanks.