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charset=UTF-8 Date: Wed, 18 Jun 2025 14:26:52 +0900 Message-Id: Subject: Re: [PATCH v5 15/23] gpu: nova-core: add falcon register definitions and base code From: "Alexandre Courbot" To: "Danilo Krummrich" Cc: "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Benno Lossin" , "John Hubbard" , "Ben Skeggs" , "Joel Fernandes" , "Timur Tabi" , "Alistair Popple" , , , , , "Lyude Paul" X-Mailer: aerc 0.20.1-0-g2ecb8770224a References: <20250612-nova-frts-v5-0-14ba7eaf166b@nvidia.com> <20250612-nova-frts-v5-15-14ba7eaf166b@nvidia.com> In-Reply-To: X-ClientProxiedBy: TYCP286CA0078.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:2b3::15) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|LV8PR12MB9134:EE_ X-MS-Office365-Filtering-Correlation-Id: a76a9f75-fc02-48ee-49c2-08ddae28bce4 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|376014|1800799024|10070799003|366016; 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Agreed, done. > > > >> +fn select_core_ga102(bar: &Bar0) -> Result { >> + let bcr_ctrl =3D regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE)= ; >> + if bcr_ctrl.core_select() !=3D PeregrineCoreSelect::Falcon { >> + regs::NV_PRISCV_RISCV_BCR_CTRL::default() >> + .set_core_select(PeregrineCoreSelect::Falcon) >> + .write(bar, E::BASE); >> + >> + util::wait_on(Duration::from_millis(10), || { > > As agreed, can you please add a brief comment to justify the timeout? Oops, for some reason I haven't addressed that part of your comment last time, sorry about that. Added `// TIMEOUT:` statements above all calls to `wait_on`. Note that sometimes the justification for these cannot be more than "arbitrarily high value indicating something went wrong". (similarly, I have added a `dma_handle_with_offset` method to `CoherentAllocation` as I said I would in v4). > >> + let r =3D regs::NV_PRISCV_RISCV_BCR_CTRL::read(bar, E::BASE= ); >> + if r.valid() { >> + Some(()) >> + } else { >> + None >> + } >> + })?; >> + } >> + >> + Ok(()) >> +} >> + >> +fn signature_reg_fuse_version_ga102( >> + dev: &device::Device, >> + bar: &Bar0, >> + engine_id_mask: u16, >> + ucode_id: u8, >> +) -> Result { >> + // The ucode fuse versions are contained in the FUSE_OPT_FPF__UCODE_VERSION >> + // registers, which are an array. Our register definition macros do= not allow us to manage them >> + // properly, so we need to hardcode their addresses for now. > > Sounds like a TODO? Yes, although it is addressed in the next iteration of the register macro (which I will send after this series), which supports register arrays. Marked this as a TODO nonetheless. > >> + >> + // Each engine has 16 ucode version registers numbered from 1 to 16= . >> + if ucode_id =3D=3D 0 || ucode_id > 16 { >> + dev_err!(dev, "invalid ucode id {:#x}", ucode_id); >> + return Err(EINVAL); >> + } >> + >> + // Base address of the FUSE registers array corresponding to the en= gine. >> + let reg_fuse_base =3D if engine_id_mask & 0x0001 !=3D 0 { >> + regs::NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION::OFFSET >> + } else if engine_id_mask & 0x0004 !=3D 0 { >> + regs::NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION::OFFSET >> + } else if engine_id_mask & 0x0400 !=3D 0 { >> + regs::NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION::OFFSET >> + } else { >> + dev_err!(dev, "unexpected engine_id_mask {:#x}", engine_id_mask= ); >> + return Err(EINVAL); >> + }; >> + >> + // Read `reg_fuse_base[ucode_id - 1]`. >> + let reg_fuse_version =3D >> + bar.read32(reg_fuse_base + ((ucode_id - 1) as usize * core::mem= ::size_of::())); >> + >> + Ok(fls_u32(reg_fuse_version)) >> +} >> + >> +fn program_brom_ga102(bar: &Bar0, params: &FalconBromP= arams) -> Result { >> + regs::NV_PFALCON2_FALCON_BROM_PARAADDR::default() >> + .set_value(params.pkc_data_offset) >> + .write(bar, E::BASE); >> + regs::NV_PFALCON2_FALCON_BROM_ENGIDMASK::default() >> + .set_value(params.engine_id_mask as u32) >> + .write(bar, E::BASE); >> + regs::NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID::default() >> + .set_ucode_id(params.ucode_id) >> + .write(bar, E::BASE); >> + regs::NV_PFALCON2_FALCON_MOD_SEL::default() >> + .set_algo(FalconModSelAlgo::Rsa3k) >> + .write(bar, E::BASE); >> + >> + Ok(()) >> +} >> + >> +pub(super) struct Ga102(PhantomData); >> + >> +impl Ga102 { >> + pub(super) fn new() -> Self { >> + Self(PhantomData) >> + } >> +} >> + >> +impl FalconHal for Ga102 { >> + fn select_core(&self, _falcon: &Falcon, bar: &Bar0) -> Result { >> + select_core_ga102::(bar) >> + } >> + >> + fn signature_reg_fuse_version( >> + &self, >> + falcon: &Falcon, >> + bar: &Bar0, >> + engine_id_mask: u16, >> + ucode_id: u8, >> + ) -> Result { >> + signature_reg_fuse_version_ga102(&falcon.dev, bar, engine_id_ma= sk, ucode_id) >> + } >> + >> + fn program_brom(&self, _falcon: &Falcon, bar: &Bar0, params: &Fa= lconBromParams) -> Result { >> + program_brom_ga102::(bar, params) >> + } > > Why are those two separate functions? Do you mean why does `program_brom` calls `program_brom_ga102`? This is so HAL methods can be re-used in other architectures. For instance, Hopper's HAL be identical to Ampere save for `select_core`, so having everything in separate functions allows the Hopper HAL to just call `program_brom_ga102`. It's a sane convention to have IMHO, maybe we should codify it via a HAL paragraph in the guidelines document?