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charset=UTF-8 Date: Mon, 28 Jul 2025 13:59:38 +0900 Message-Id: Subject: Re: [PATCH v2 01/19] gpu: nova-core: register: minor grammar and spelling fixes From: "Alexandre Courbot" To: "Daniel Almeida" Cc: "Danilo Krummrich" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Beata Michalska" , , , , , "John Hubbard" , , "Nouveau" X-Mailer: aerc 0.20.1-0-g2ecb8770224a-dirty References: <20250718-nova-regs-v2-0-7b6a762aa1cd@nvidia.com> <20250718-nova-regs-v2-1-7b6a762aa1cd@nvidia.com> In-Reply-To: X-ClientProxiedBy: TYCP286CA0242.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:456::9) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|DM4PR12MB9733:EE_ X-MS-Office365-Filtering-Correlation-Id: efcf3bf2-b9b9-4f62-6a45-08ddcd939001 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|10070799003|376014|7416014|366016; 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On Sat Jul 26, 2025 at 1:14 AM JST, Daniel Almeida wrote: > Hi Alex. Thank you and John for working on this in general. It will be us= eful > for the whole ecosystem! :)=20 > >> On 18 Jul 2025, at 04:26, Alexandre Courbot wrote: >>=20 >> From: John Hubbard >>=20 >> There is only one top-level macro in this file at the moment, but the >> "macros.rs" file name allows for more. Change the wording so that it >> will remain valid even if additional macros are added to the file. >>=20 >> Fix a couple of spelling errors and grammatical errors, and break up a >> run-on sentence, for clarity. >>=20 >> Cc: Alexandre Courbot >> Cc: Danilo Krummrich >> Signed-off-by: John Hubbard >> Signed-off-by: Alexandre Courbot >> --- >> drivers/gpu/nova-core/regs/macros.rs | 14 +++++++------- >> 1 file changed, 7 insertions(+), 7 deletions(-) >>=20 >> diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-cor= e/regs/macros.rs >> index cdf668073480ed703c89ffa8628f5c9de6494687..864d1e83bed2979f5661e038= f4c9fd87d33f69a7 100644 >> --- a/drivers/gpu/nova-core/regs/macros.rs >> +++ b/drivers/gpu/nova-core/regs/macros.rs >> @@ -1,17 +1,17 @@ >> // SPDX-License-Identifier: GPL-2.0 >>=20 >> -//! Macro to define register layout and accessors. >> +//! `register!` macro to define register layout and accessors. > > I would have kept this line as-is. Users will most likely know the name o= f the > macro already. At this point, they will be looking for what it does, so > mentioning "register" here is a bit redundant IMHO. > >> //! >> //! A single register typically includes several fields, which are acces= sed through a combination >> //! of bit-shift and mask operations that introduce a class of potential= mistakes, notably because >> //! not all possible field values are necessarily valid. >> //! >> -//! The macro in this module allow to define, using an intruitive and r= eadable syntax, a dedicated >> -//! type for each register with its own field accessors that can return= an error is a field's value >> -//! is invalid. >> +//! The `register!` macro in this module provides an intuitive and read= able syntax for defining a >> +//! dedicated type for each register. Each such type comes with its own= field accessors that can >> +//! return an error if a field's value is invalid. >>=20 >> -/// Defines a dedicated type for a register with an absolute offset, al= ongside with getter and >> -/// setter methods for its fields and methods to read and write it from= an `Io` region. >> +/// Defines a dedicated type for a register with an absolute offset, in= cluding getter and setter >> +/// methods for its fields and methods to read and write it from an `Io= ` region. > > +cc Steven Price, > > Sorry for hijacking this patch, but I think that we should be more flexib= le and > allow for non-literal offsets in the macro. > > In Tyr, for example, some of the offsets need to be computed at runtime, = i.e.: > > +pub(crate) struct AsRegister(usize); > + > +impl AsRegister { > + fn new(as_nr: usize, offset: usize) -> Result { > + if as_nr >=3D 32 { > + Err(EINVAL) > + } else { > + Ok(AsRegister(mmu_as(as_nr) + offset)) > + } > + } > > Or: > > +pub(crate) struct Doorbell(usize); > + > +impl Doorbell { > + pub(crate) fn new(doorbell_id: usize) -> Self { > + Doorbell(0x80000 + (doorbell_id * 0x10000)) > + } > > I don't think this will work with the current macro, JFYI. IIUC from the comments on the next patches, your need is covered with the relative and array registers definitions, is that correct?