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charset=UTF-8 Date: Mon, 28 Jul 2025 20:43:15 +0900 Message-Id: Cc: "Danilo Krummrich" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "Beata Michalska" , , , , , "John Hubbard" , "Nouveau" Subject: Re: [PATCH v2 01/19] gpu: nova-core: register: minor grammar and spelling fixes From: "Alexandre Courbot" To: "Steven Price" , "Daniel Almeida" X-Mailer: aerc 0.20.1-0-g2ecb8770224a-dirty References: <20250718-nova-regs-v2-0-7b6a762aa1cd@nvidia.com> <20250718-nova-regs-v2-1-7b6a762aa1cd@nvidia.com> In-Reply-To: X-ClientProxiedBy: TYCPR01CA0038.jpnprd01.prod.outlook.com (2603:1096:405:1::26) To BY5PR12MB3986.namprd12.prod.outlook.com (2603:10b6:a03:195::27) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|LV3PR12MB9118:EE_ X-MS-Office365-Filtering-Correlation-Id: 9070399d-4360-4b23-6dd1-08ddcdcbf1f2 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|10070799003|366016|7416014|376014|1800799024; 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Thank you and John for working on this in general. It will be = useful >>> for the whole ecosystem! :)=20 >>> >>>> On 18 Jul 2025, at 04:26, Alexandre Courbot wrot= e: >>>> >>>> From: John Hubbard >>>> >>>> There is only one top-level macro in this file at the moment, but the >>>> "macros.rs" file name allows for more. Change the wording so that it >>>> will remain valid even if additional macros are added to the file. >>>> >>>> Fix a couple of spelling errors and grammatical errors, and break up a >>>> run-on sentence, for clarity. >>>> >>>> Cc: Alexandre Courbot >>>> Cc: Danilo Krummrich >>>> Signed-off-by: John Hubbard >>>> Signed-off-by: Alexandre Courbot >>>> --- >>>> drivers/gpu/nova-core/regs/macros.rs | 14 +++++++------- >>>> 1 file changed, 7 insertions(+), 7 deletions(-) >>>> >>>> diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-c= ore/regs/macros.rs >>>> index cdf668073480ed703c89ffa8628f5c9de6494687..864d1e83bed2979f5661e0= 38f4c9fd87d33f69a7 100644 >>>> --- a/drivers/gpu/nova-core/regs/macros.rs >>>> +++ b/drivers/gpu/nova-core/regs/macros.rs >>>> @@ -1,17 +1,17 @@ >>>> // SPDX-License-Identifier: GPL-2.0 >>>> >>>> -//! Macro to define register layout and accessors. >>>> +//! `register!` macro to define register layout and accessors. >>> >>> I would have kept this line as-is. Users will most likely know the name= of the >>> macro already. At this point, they will be looking for what it does, so >>> mentioning "register" here is a bit redundant IMHO. >>> >>>> //! >>>> //! A single register typically includes several fields, which are acc= essed through a combination >>>> //! of bit-shift and mask operations that introduce a class of potenti= al mistakes, notably because >>>> //! not all possible field values are necessarily valid. >>>> //! >>>> -//! The macro in this module allow to define, using an intruitive and= readable syntax, a dedicated >>>> -//! type for each register with its own field accessors that can retu= rn an error is a field's value >>>> -//! is invalid. >>>> +//! The `register!` macro in this module provides an intuitive and re= adable syntax for defining a >>>> +//! dedicated type for each register. Each such type comes with its o= wn field accessors that can >>>> +//! return an error if a field's value is invalid. >>>> >>>> -/// Defines a dedicated type for a register with an absolute offset, = alongside with getter and >>>> -/// setter methods for its fields and methods to read and write it fr= om an `Io` region. >>>> +/// Defines a dedicated type for a register with an absolute offset, = including getter and setter >>>> +/// methods for its fields and methods to read and write it from an `= Io` region. >>> >>> +cc Steven Price, >>> >>> Sorry for hijacking this patch, but I think that we should be more flex= ible and >>> allow for non-literal offsets in the macro. >>> >>> In Tyr, for example, some of the offsets need to be computed at runtime= , i.e.: >>> >>> +pub(crate) struct AsRegister(usize); >>> + >>> +impl AsRegister { >>> + fn new(as_nr: usize, offset: usize) -> Result { >>> + if as_nr >=3D 32 { >>> + Err(EINVAL) >>> + } else { >>> + Ok(AsRegister(mmu_as(as_nr) + offset)) >>> + } >>> + } >>> >>> Or: >>> >>> +pub(crate) struct Doorbell(usize); >>> + >>> +impl Doorbell { >>> + pub(crate) fn new(doorbell_id: usize) -> Self { >>> + Doorbell(0x80000 + (doorbell_id * 0x10000)) >>> + } >>> >>> I don't think this will work with the current macro, JFYI. >>=20 >> IIUC from the comments on the next patches, your need is covered with >> the relative and array registers definitions, is that correct? > > My Rust is somewhat shaky, but I believe "non-contiguous register=20 > arrays" will do what we want. Although I'll admit it would be neater for= =20 > the likes of the AS registers if there was a way to define a "block" of=20 > registers and then use an array of blocks. Something vaguely like this=20 > (excuse the poor Rust): > > register_block!(MMU_AS_CONTROL @ 0x2400[16 ; 64], "MMU Address Space regi= sters" { > register!(TRANSTAB @ 0x0000, "Translation table base address" { > 31:0 base as u32; > }); > register!(MEMATTR @ 0x0008, "Memory attributes" { > 7:0 attr0 as u8; > 7:0 attr1 as u8; > // ... > }); > // More registers > }); I can think of two ways to achieve something similar using the current patchset: - As you mentioned, a set of non-contiguous register arrays. This should work rather well, as you could just do `MMU_AS_CONTROL_MEMATTR::read(bar, 4)` to read the `MMU_AS_CONTROL_MEMATT= R` register of the 5th instance, with compile-time bound validation. It's not what register arrays are for originally, but it does the job. - As a set of relative offset registers sharing the same group. This is more in line with the idea of a register block, but it also means that each instance needs to have its own type declared, which is a bit cumbersome but can be mitigated with a macro. More inconvenient if the fact that you cannot address using a simple number anymore... The idea of register blocks is interesting. I wonder how that would translate in terms of access to invididual registers, i.e. does the block end up just being a prefix into the full register name, or is it something else? From your example declaration I picture that accesses would look something like `MMU_AS_CONTROL[4]::MEMATTR::read(bar)`, which ngl looks great, but I also cannot think of a construct that would allow such a syntax... Happy to think more about it though.