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charset=UTF-8 Date: Fri, 26 Sep 2025 16:27:04 +0900 Message-Id: Subject: Re: [PATCH v2 06/10] gpu: nova-core: gsp: Create rmargs From: "Alexandre Courbot" To: "Alistair Popple" , , , , Cc: "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "John Hubbard" , "Joel Fernandes" , "Timur Tabi" , , X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20250922113026.3083103-1-apopple@nvidia.com> <20250922113026.3083103-7-apopple@nvidia.com> In-Reply-To: <20250922113026.3083103-7-apopple@nvidia.com> X-ClientProxiedBy: TYWPR01CA0032.jpnprd01.prod.outlook.com (2603:1096:400:aa::19) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|IA0PR12MB7604:EE_ X-MS-Office365-Filtering-Correlation-Id: dfdc7d99-0b6d-4297-5edd-08ddfcce1985 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|10070799003|7416014|376014; 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The rmargs > structure contains arguments to configure the GSP message/command queue > location. > > These are mapped for coherent DMA and added to the libos data structure > for access when booting GSP. > > Signed-off-by: Alistair Popple > > --- > > Changes for v2: > - Rebased on Alex's latest series > --- > drivers/gpu/nova-core/gsp.rs | 29 +++++++++++++++- > drivers/gpu/nova-core/gsp/cmdq.rs | 14 ++++++-- > drivers/gpu/nova-core/gsp/fw.rs | 19 +++++++++++ > .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 33 +++++++++++++++++++ > 4 files changed, 91 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp.rs > index 3d4028d67d2e..bb08bd537ec4 100644 > --- a/drivers/gpu/nova-core/gsp.rs > +++ b/drivers/gpu/nova-core/gsp.rs > @@ -17,7 +17,10 @@ > use crate::fb::FbLayout; > use crate::gsp::cmdq::GspCmdq; > =20 > -use fw::LibosMemoryRegionInitArgument; > +use fw::{ > + LibosMemoryRegionInitArgument, GSP_ARGUMENTS_CACHED, GSP_SR_INIT_ARG= UMENTS, > + MESSAGE_QUEUE_INIT_ARGUMENTS, > +}; > =20 > pub(crate) mod cmdq; > =20 > @@ -33,6 +36,7 @@ pub(crate) struct Gsp { > pub logintr: CoherentAllocation, > pub logrm: CoherentAllocation, > pub cmdq: GspCmdq, > + rmargs: CoherentAllocation, > } > =20 > /// Creates a self-mapping page table for `obj` at its beginning. > @@ -90,12 +94,35 @@ pub(crate) fn new(pdev: &pci::Device) = -> Result =20 > // Creates its own PTE array > let cmdq =3D GspCmdq::new(dev)?; > + let rmargs =3D > + create_coherent_dma_object::(dev, "RMA= RGS", 1, &mut libos, 3)?; > + let (shared_mem_phys_addr, cmd_queue_offset, stat_queue_offset) = =3D cmdq.get_cmdq_offsets(); > + > + dma_write!( > + rmargs[0].messageQueueInitArguments =3D MESSAGE_QUEUE_INIT_A= RGUMENTS { > + sharedMemPhysAddr: shared_mem_phys_addr, > + pageTableEntryCount: cmdq.nr_ptes, > + cmdQueueOffset: cmd_queue_offset, > + statQueueOffset: stat_queue_offset, > + ..Default::default() > + } > + )?; > + dma_write!( > + rmargs[0].srInitArguments =3D GSP_SR_INIT_ARGUMENTS { > + oldLevel: 0, > + flags: 0, > + bInPMTransition: 0, > + ..Default::default() > + } > + )?; > + dma_write!(rmargs[0].bDmemStack =3D 1)?; Wrapping our bindings is going to help clean up this code as well. First, types named in CAPITALS_SNAKE_CASE are not idiomatic Rust and look like constants. And it's not even like the bindings types are consistently named that way, since we also have e.g. `GspFwWprMeta` - so let's give them a proper public name and bring some consistency at the same time. This will make all the fields from `GSP_ARGUMENTS_CACHED` invisible to this module as they should be, so the wrapping `GspArgumentsCached` type should then have a constructor that receives a referene to the command queue and takes the information is needs from it, similarly to `GspFwWprMeta`. This will reduce the 3 `dma_write!` into a single one. Then we should remove `get_cmdq_offsets`, which is super confusing. I am also not fond of `cmdq.nr_ptes`. More on them below. > =20 > Ok(try_pin_init!(Self { > libos, > loginit, > logintr, > logrm, > + rmargs, > cmdq, > })) > } > diff --git a/drivers/gpu/nova-core/gsp/cmdq.rs b/drivers/gpu/nova-core/gs= p/cmdq.rs > index a9ba1a4c73d8..9170ccf4a064 100644 > --- a/drivers/gpu/nova-core/gsp/cmdq.rs > +++ b/drivers/gpu/nova-core/gsp/cmdq.rs > @@ -99,7 +99,6 @@ fn new(dev: &device::Device) -> Result { > Ok(Self(gsp_mem)) > } > =20 > - #[expect(unused)] > fn dma_handle(&self) -> DmaAddress { > self.0.dma_handle() > } > @@ -218,7 +217,7 @@ pub(crate) struct GspCmdq { > dev: ARef, > seq: u32, > gsp_mem: DmaGspMem, > - pub _nr_ptes: u32, > + pub nr_ptes: u32, > } > =20 > impl GspCmdq { > @@ -231,7 +230,7 @@ pub(crate) fn new(dev: &device::Device= ) -> Result { > dev: dev.into(), > seq: 0, > gsp_mem, > - _nr_ptes: nr_ptes as u32, > + nr_ptes: nr_ptes as u32, > }) > } > =20 > @@ -382,6 +381,15 @@ pub(crate) fn receive_msg_from_gsp( > .advance_cpu_read_ptr(msg_header.rpc.length.div_ceil(GSP_PAG= E_SIZE as u32)); > result > } > + > + pub(crate) fn get_cmdq_offsets(&self) -> (u64, u64, u64) { > + ( > + self.gsp_mem.dma_handle(), > + core::mem::offset_of!(Msgq, msgq) as u64, > + (core::mem::offset_of!(GspMem, gspq) - core::mem::offset_of!= (GspMem, cpuq) > + + core::mem::offset_of!(Msgq, msgq)) as u64, > + ) > + } So this thing returns 3 u64s, one of which is actually a DMA handle, while the two others are technically constants. The only thing that needs to be inferred at runtime is the DMA handle - all the rest is static. So we can make the two last returned values associated constants of `GspCmdq`: impl GspCmdq { /// Offset of the data after the PTEs. const POST_PTE_OFFSET: usize =3D core::mem::offset_of!(GspMem, cpuq); /// Offset of command queue ring buffer. pub(crate) const CMDQ_OFFSET: usize =3D core::mem::offset_of!(GspMem,= cpuq) + core::mem::offset_of!(Msgq, msgq) - Self::POST_PTE_OFFSET; /// Offset of message queue ring buffer. pub(crate) const STATQ_OFFSET: usize =3D core::mem::offset_of!(GspMem= , gspq) + core::mem::offset_of!(Msgq, msgq) - Self::POST_PTE_OFFSET; `GspArgumentsCached::new` can then import `GspCmdq` and use these to initialize its corresponding members. Remains `nr_ptes`. It was introduced in the previous patch as follows: let nr_ptes =3D size_of::() >> GSP_PAGE_SHIFT; Which turns out to also be a constant! So let's add it next to the others: impl GspCmdq { ... /// Number of page table entries for the GSP shared region. pub(crate) const NUM_PTES: usize =3D size_of::() >> GSP_PAGE_SH= IFT; And you can remove `GspCmdq::nr_ptes` altogether. With this, `GspArgumentsCached::new` can take a reference to the `GspCmdq` to initialize from, grab its DMA handle, and initialize everything else using the constants we defined above. We remove a bunch of inconsistently-named imports from `gsp.rs`, and replace firmware-dependent incantations to initialize our GSP arguments with a single constructor call that tells exactly what it does in a single line.