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charset=UTF-8 Date: Mon, 29 Sep 2025 23:54:50 +0900 Message-Id: To: "Alistair Popple" , "Alexandre Courbot" Cc: "Lyude Paul" , , , , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , "David Airlie" , "Simona Vetter" , "Maarten Lankhorst" , "Maxime Ripard" , "Thomas Zimmermann" , "John Hubbard" , "Joel Fernandes" , "Timur Tabi" , , Subject: Re: [PATCH v2 03/10] gpu: nova-core: gsp: Create wpr metadata From: "Alexandre Courbot" X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20250922113026.3083103-1-apopple@nvidia.com> <20250922113026.3083103-4-apopple@nvidia.com> In-Reply-To: X-ClientProxiedBy: OS0PR01CA0132.jpnprd01.prod.outlook.com (2603:1096:604:9b::31) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|BL3PR12MB6476:EE_ X-MS-Office365-Filtering-Correlation-Id: c141a810-478c-4388-bfde-08ddff682672 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|7416014|366016|376014|10070799003|1800799024; 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These are passed in= a >> >> struct which the GSP transfers via DMA. Create this struct and get a >> >> handle to it for future use when booting the GSP. >> >>=20 >> >> Signed-off-by: Alistair Popple >> >>=20 >> >> --- >> >>=20 >> >> Changes for v2: >> >> - Rebased on Alex's latest version >> >> --- >> >> drivers/gpu/nova-core/fb.rs | 1 - >> >> drivers/gpu/nova-core/firmware/gsp.rs | 3 +- >> >> drivers/gpu/nova-core/firmware/riscv.rs | 6 +- >> >> drivers/gpu/nova-core/gsp.rs | 1 + >> >> drivers/gpu/nova-core/gsp/boot.rs | 7 +++ >> >> drivers/gpu/nova-core/gsp/fw.rs | 63 +++++++++++++++++= +- >> >> .../gpu/nova-core/gsp/fw/r570_144/bindings.rs | 2 + >> >> 7 files changed, 75 insertions(+), 8 deletions(-) >> >>=20 >> >> diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.r= s >> >> index 4d6a1f452183..5580498ba2fb 100644 >> >> --- a/drivers/gpu/nova-core/fb.rs >> >> +++ b/drivers/gpu/nova-core/fb.rs >> >> @@ -87,7 +87,6 @@ pub(crate) fn unregister(&self, bar: &Bar0) { >> >> /// >> >> /// Contains ranges of GPU memory reserved for a given purpose durin= g the GSP boot process. >> >> #[derive(Debug)] >> >> -#[expect(dead_code)] >> >> pub(crate) struct FbLayout { >> >> /// Range of the framebuffer. Starts at `0`. >> >> pub(crate) fb: Range, >> >> diff --git a/drivers/gpu/nova-core/firmware/gsp.rs b/drivers/gpu/nova= -core/firmware/gsp.rs >> >> index 9654810834d9..67b85e1db27d 100644 >> >> --- a/drivers/gpu/nova-core/firmware/gsp.rs >> >> +++ b/drivers/gpu/nova-core/firmware/gsp.rs >> >> @@ -127,7 +127,7 @@ pub(crate) struct GspFirmware { >> >> /// Size in bytes of the firmware contained in [`Self::fw`]. >> >> pub size: usize, >> >> /// Device-mapped GSP signatures matching the GPU's [`Chipset`]. >> >> - signatures: DmaObject, >> >> + pub signatures: DmaObject, >> >> /// GSP bootloader, verifies the GSP firmware before loading and= running it. >> >> pub bootloader: RiscvFirmware, >> >> } >> >> @@ -212,7 +212,6 @@ pub(crate) fn new<'a, 'b>( >> >> })) >> >> } >> >> =20 >> >> - #[expect(unused)] >> >> /// Returns the DMA handle of the radix3 level 0 page table. >> >> pub(crate) fn radix3_dma_handle(&self) -> DmaAddress { >> >> self.level0.dma_handle() >> >> diff --git a/drivers/gpu/nova-core/firmware/riscv.rs b/drivers/gpu/no= va-core/firmware/riscv.rs >> >> index b90acfc81e78..dec33d2b631a 100644 >> >> --- a/drivers/gpu/nova-core/firmware/riscv.rs >> >> +++ b/drivers/gpu/nova-core/firmware/riscv.rs >> >> @@ -53,11 +53,11 @@ fn new(bin_fw: &BinFirmware<'_>) -> Result = { >> >> #[expect(unused)] >> >> pub(crate) struct RiscvFirmware { >> >> /// Offset at which the code starts in the firmware image. >> >> - code_offset: u32, >> >> + pub code_offset: u32, >> >> /// Offset at which the data starts in the firmware image. >> >> - data_offset: u32, >> >> + pub data_offset: u32, >> >> /// Offset at which the manifest starts in the firmware image. >> >> - manifest_offset: u32, >> >> + pub manifest_offset: u32, >> >> /// Application version. >> >> app_version: u32, >> >> /// Device-mapped firmware image. >> >> diff --git a/drivers/gpu/nova-core/gsp.rs b/drivers/gpu/nova-core/gsp= .rs >> >> index 0185f66971ff..2daa46f2a514 100644 >> >> --- a/drivers/gpu/nova-core/gsp.rs >> >> +++ b/drivers/gpu/nova-core/gsp.rs >> >> @@ -13,6 +13,7 @@ >> >> use kernel::ptr::Alignment; >> >> use kernel::transmute::{AsBytes, FromBytes}; >> >> =20 >> >> +use crate::fb::FbLayout; >> >> use fw::LibosMemoryRegionInitArgument; >> >> =20 >> >> pub(crate) const GSP_PAGE_SHIFT: usize =3D 12; >> >> diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-cor= e/gsp/boot.rs >> >> index fb22508128c4..1d2448331d7a 100644 >> >> --- a/drivers/gpu/nova-core/gsp/boot.rs >> >> +++ b/drivers/gpu/nova-core/gsp/boot.rs >> >> @@ -1,6 +1,8 @@ >> >> // SPDX-License-Identifier: GPL-2.0 >> >> =20 >> >> use kernel::device; >> >> +use kernel::dma::CoherentAllocation; >> >> +use kernel::dma_write; >> >> use kernel::pci; >> >> use kernel::prelude::*; >> >> =20 >> >> @@ -14,6 +16,7 @@ >> >> FIRMWARE_VERSION, >> >> }; >> >> use crate::gpu::Chipset; >> >> +use crate::gsp::GspFwWprMeta; >> >> use crate::regs; >> >> use crate::vbios::Vbios; >> >> =20 >> >> @@ -132,6 +135,10 @@ pub(crate) fn boot( >> >> bar, >> >> )?; >> >> =20 >> >> + let wpr_meta =3D >> >> + CoherentAllocation::::alloc_coherent(dev, = 1, GFP_KERNEL | __GFP_ZERO)?; >> >> + dma_write!(wpr_meta[0] =3D GspFwWprMeta::new(&gsp_fw, &fb_la= yout))?; >> > >> > Not something I think we need to block this series on, but this line d= oes make >> > me wonder if we should have a variant of dma_write!() that uses >> > CoherentAllocation::write(), since I think that would actually be fast= er then >> > calling dma_write!() here. >>=20 >> Can you elaborate a bit on this idea? Would it be faster because it uses >> a non-volatile write in this case? >>=20 >> On a related note, I wish we could make all these accesses to >> single-instance coherent allocations non-fallible, as this is a pattern >> we use often in Nova and the only thing that can fail is >> `item_from_index`, which we know at build-time is valid as we are >> accessing the first element. >>=20 >> So if we enforced a rule that `count` must be >=3D 0 in >> `CoherentAllocation::alloc_attrs` (which is not currently enforced but >> would make sense imho), we could maybe add a new variant to >> `dma_read/write` that matches a non-indexed expression, and makes a >> non-fallible access to the first element of the allocation? How does >> that sound? > > Would this have to be limited to the first element though? I assume we co= uld > make a CoherentAllocation variant where the number of elements is a compi= le time > constant and therefore dma_read/write on those would be infallible except= at > build time. Oh yeah, we would have to try and write such a variant but AFAICT this should work nicely.