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Date: Thu, 09 Oct 2025 15:02:39 +0200
Message-Id: <DDDT8EEG7E8B.27YT6QAFIS9GK@kernel.org>
From: "Danilo Krummrich" <dakr@kernel.org>
Subject: Re: [PATCH v6 0/5] Introduce bitfield and move register macro to
 rust/kernel/
Cc: "Alexandre Courbot" <acourbot@nvidia.com>, "Yury Norov"
 <yury.norov@gmail.com>, "linux-kernel@vger.kernel.org"
 <linux-kernel@vger.kernel.org>, "rust-for-linux@vger.kernel.org"
 <rust-for-linux@vger.kernel.org>, "dri-devel@lists.freedesktop.org"
 <dri-devel@lists.freedesktop.org>, "Alistair Popple" <apopple@nvidia.com>,
 "Miguel Ojeda" <ojeda@kernel.org>, "Alex Gaynor" <alex.gaynor@gmail.com>,
 "Boqun Feng" <boqun.feng@gmail.com>, "Gary Guo" <gary@garyguo.net>,
 "bjorn3_gh@protonmail.com" <bjorn3_gh@protonmail.com>, "Benno Lossin"
 <lossin@kernel.org>, "Andreas Hindborg" <a.hindborg@kernel.org>, "Alice
 Ryhl" <aliceryhl@google.com>, "Trevor Gross" <tmgross@umich.edu>, "David
 Airlie" <airlied@gmail.com>, "Simona Vetter" <simona@ffwll.ch>, "Maarten
 Lankhorst" <maarten.lankhorst@linux.intel.com>, "Maxime Ripard"
 <mripard@kernel.org>, "Thomas Zimmermann" <tzimmermann@suse.de>, "John
 Hubbard" <jhubbard@nvidia.com>, "Timur Tabi" <ttabi@nvidia.com>,
 "joel@joelfernandes.org" <joel@joelfernandes.org>, "Elle Rhumsaa"
 <elle@weathered-steel.dev>, "Daniel Almeida"
 <daniel.almeida@collabora.com>, "Andrea Righi" <arighi@nvidia.com>,
 "nouveau@lists.freedesktop.org" <nouveau@lists.freedesktop.org>
To: "Joel Fernandes" <joelagnelf@nvidia.com>
References: <695CCDCE-A205-4557-AA15-6F102B8CCF0C@nvidia.com>
 <DDCV84IJHUML.126CB1CT0XMX5@kernel.org>
 <22e8c33c-b444-4f58-b7ec-6374475e05be@nvidia.com>
In-Reply-To: <22e8c33c-b444-4f58-b7ec-6374475e05be@nvidia.com>

On Thu Oct 9, 2025 at 2:24 AM CEST, Joel Fernandes wrote:
> On 10/8/2025 6:23 AM, Danilo Krummrich wrote:
>> On Wed Oct 8, 2025 at 1:37 AM CEST, Joel Fernandes wrote:
>>> The Nvidia GPU architecture is little-endian (including MMU structures =
in VRAM).
>>=20
>> Yes, I'm aware (and I'd assume that there is no reason to ever change th=
at).
>>=20
>> Just for the complete picture, there's also some endianness switch in th=
e
>> NV_PMC_BOOT_1 register I think?
>
> You are referring to old GPUs. NV_PMC_BOOT_1 does not have endianness swi=
tch for
> Turing and later.

Ok, then there's no point in considering big-endian CPUs.

> If we want to add a Kconfig patch enabling Nova only on x86/ARM, that'll =
be Ok
> with me.

I don't see why we'd constrain it to x86 and ARM, but we should indeed cons=
train
it to little-endian architectures.