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Date: Fri, 17 Oct 2025 12:56:34 +0200
Message-Id: <DDKJK7SXG83N.2YZYITMDGTHP@kernel.org>
Cc: <rust-for-linux@vger.kernel.org>, <bhelgaas@google.com>,
 <kwilczynski@kernel.org>, <ojeda@kernel.org>, <alex.gaynor@gmail.com>,
 <boqun.feng@gmail.com>, <gary@garyguo.net>, <bjorn3_gh@protonmail.com>,
 <lossin@kernel.org>, <a.hindborg@kernel.org>, <aliceryhl@google.com>,
 <tmgross@umich.edu>, <linux-pci@vger.kernel.org>,
 <linux-kernel@vger.kernel.org>, <cjia@nvidia.com>, <smitra@nvidia.com>,
 <ankita@nvidia.com>, <aniketa@nvidia.com>, <kwankhede@nvidia.com>,
 <targupta@nvidia.com>, <zhiwang@kernel.org>, <acourbot@nvidia.com>,
 <joelagnelf@nvidia.com>, <jhubbard@nvidia.com>, <markus.probst@posteo.de>
To: "Zhi Wang" <zhiw@nvidia.com>
From: "Danilo Krummrich" <dakr@kernel.org>
Subject: Re: [PATCH v2 1/5] rust/io: factor common I/O helpers into Io trait
 and specialize Mmio<SIZE>
References: <20251016210250.15932-1-zhiw@nvidia.com>
 <20251016210250.15932-2-zhiw@nvidia.com>
In-Reply-To: <20251016210250.15932-2-zhiw@nvidia.com>

On Thu Oct 16, 2025 at 11:02 PM CEST, Zhi Wang wrote:
> diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core=
/regs/macros.rs
> index 8058e1696df9..c2a6547d58cd 100644
> --- a/drivers/gpu/nova-core/regs/macros.rs
> +++ b/drivers/gpu/nova-core/regs/macros.rs
> @@ -609,7 +609,7 @@ impl $name {
>              /// Read the register from its address in `io`.
>              #[inline(always)]
>              pub(crate) fn read<const SIZE: usize, T>(io: &T) -> Self whe=
re
> -                T: ::core::ops::Deref<Target =3D ::kernel::io::Io<SIZE>>=
,
> +                T: ::core::ops::Deref<Target =3D ::kernel::io::Mmio<SIZE=
>>,

This should be

	T: ::core::ops::Deref<Target =3D I>,
	I: ::kernel::io::Io<SIZE>,

instead, otherwise register!() only works for MMIO, but it should work for =
any
I/O backend.

> +impl<const SIZE: usize> Io<SIZE> for Mmio<SIZE> {
> +    /// Returns the base address of this mapping.
> +    #[inline]
> +    fn addr(&self) -> usize {
> +        self.0.addr()
> +    }
> +
> +    /// Returns the maximum size of this mapping.
> +    #[inline]
> +    fn maxsize(&self) -> usize {
> +        self.0.maxsize()
> +    }
> +}

The I/O trait should contain the corresponding read/write accessors, otherw=
ise
we can't easily wire up the register!() macro with arbitrary I/O backends.

I think more specific things, such as relaxed operations can remain MMIO
specific, but all the {try_}{read,write}{8,16,32,64} accessors should be pa=
rt of
the I/O trait.