* [PATCH RESEND v4 0/4] rust: pci: add config space read/write support
@ 2025-11-04 14:27 Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 1/4] rust: io: factor common I/O helpers into Io trait Zhi Wang
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Zhi Wang @ 2025-11-04 14:27 UTC (permalink / raw)
To: rust-for-linux, linux-pci, linux-kernel
Cc: dakr, aliceryhl, bhelgaas, kwilczynski, ojeda, alex.gaynor,
boqun.feng, gary, bjorn3_gh, lossin, a.hindborg, tmgross,
markus.probst, helgaas, cjia, smitra, ankita, aniketa, kwankhede,
targupta, acourbot, joelagnelf, jhubbard, zhiwang, Zhi Wang
In the NVIDIA vGPU RFC [1], the PCI configuration space access is
required in nova-core for preparing gspVFInfo when vGPU support is
enabled. This series is the following up of the discussion with Danilo
for how to introduce support of PCI configuration space access in Rust
PCI abstractions.
v4:
- Refactor the SIZE constant to be an associated constant. (Alice)
- Remove the default method implementations in the Io trait. (Alice)
- Make cfg_size() private. (Danilo/Bjorn)
- Implement the infallible accessors of ConfigSpace. (Danilo)
- Create a new Io64 trait specifically for 64-bit accessors. (Danilo)
- Provide two separate methods for driver: config_space() and
config_space_extended(). (Danilo)
- Update the sample driver to test the infallible accessors. (Danilo)
v3:
- Turn offset_valid() into a private function of kernel::io:Io. (Alex)
- Separate try and non-try variants. (Danilo)
- Move all the {try_}{read,write}{8,16,32,64} accessors to the I/O trait.
(Danilo)
- Replace the hardcoded MMIO type constraint with a generic trait bound
so that register! macro can be used in other places. (Danilo)
- Fix doctest. (John)
- Add an enum for PCI configuration space size. (Danilo)
- Refine the patch comments. (Bjorn)
v2:
- Factor out common trait as 'Io' and keep the rest routines in original
'Io' as 'Mmio'. (Danilo)
- Rename 'IoRaw' to 'MmioRaw'. Update the bus MMIO implementation to use
'MmioRaw'.
- Introduce pci::Device<Bound>::config_space(). (Danilo)
- Implement both infallible and fallible read/write routines, the device
driver decicdes which version should be used.
This ideas of this series are:
- Factor out a common trait IoRegion for other accessors to share the
same compiling/runtime check like before.
- Factor the MMIO read/write macros from the define_read! and
define_write! macros. Thus, define_{read, write}! can be used in other
backend.
In detail:
* Introduce `call_mmio_read!` and `call_mmio_write!` helper macros
to encapsulate the unsafe FFI calls.
* Update `define_read!` and `define_write!` macros to delegate to
the call macros.
* Export `define_read` and `define_write` so they can be reused
for other I/O backends (e.g. PCI config space).
- Add a helper to query configuration space size. This is mostly for
runtime check.
- Implement the PCI configuration space access backend in PCI
Abstractions.
- Add tests for config space routines in rust PCI sample driver.
[1] https://lore.kernel.org/all/20250903221111.3866249-1-zhiw@nvidia.com/
Zhi Wang (4):
rust: io: factor common I/O helpers into Io trait
rust: io: factor out MMIO read/write macros
rust: pci: add config space read/write support
sample: rust: pci: add tests for config space routines
drivers/gpu/nova-core/regs/macros.rs | 90 ++++----
drivers/gpu/nova-core/vbios.rs | 1 +
rust/kernel/devres.rs | 12 +-
rust/kernel/io.rs | 298 ++++++++++++++++++++-------
rust/kernel/io/mem.rs | 16 +-
rust/kernel/io/poll.rs | 4 +-
rust/kernel/pci.rs | 156 +++++++++++++-
samples/rust/rust_driver_pci.rs | 48 ++++-
8 files changed, 483 insertions(+), 142 deletions(-)
--
2.51.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH RESEND v4 1/4] rust: io: factor common I/O helpers into Io trait
2025-11-04 14:27 [PATCH RESEND v4 0/4] rust: pci: add config space read/write support Zhi Wang
@ 2025-11-04 14:27 ` Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 2/4] rust: io: factor out MMIO read/write macros Zhi Wang
` (2 subsequent siblings)
3 siblings, 0 replies; 11+ messages in thread
From: Zhi Wang @ 2025-11-04 14:27 UTC (permalink / raw)
To: rust-for-linux, linux-pci, linux-kernel
Cc: dakr, aliceryhl, bhelgaas, kwilczynski, ojeda, alex.gaynor,
boqun.feng, gary, bjorn3_gh, lossin, a.hindborg, tmgross,
markus.probst, helgaas, cjia, smitra, ankita, aniketa, kwankhede,
targupta, acourbot, joelagnelf, jhubbard, zhiwang, Zhi Wang
The previous Io<SIZE> type combined both the generic I/O access helpers
and MMIO implementation details in a single struct.
To establish a cleaner layering between the I/O interface and its concrete
backends, paving the way for supporting additional I/O mechanisms in the
future, Io<SIZE> need to be factored.
Factor the common helpers into a new Io trait, and move the MMIO-specific
logic into a dedicated Mmio<SIZE> type implementing that trait. Rename the
IoRaw to MmioRaw and update the bus MMIO implementations to use MmioRaw.
No functional change intended.
Cc: Alexandre Courbot <acourbot@nvidia.com>
Cc: Bjorn Helgaas <helgaas@kernel.org>
Cc: Danilo Krummrich <dakr@kernel.org>
Cc: John Hubbard <jhubbard@nvidia.com>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
drivers/gpu/nova-core/regs/macros.rs | 90 ++++++----
drivers/gpu/nova-core/vbios.rs | 1 +
rust/kernel/devres.rs | 12 +-
rust/kernel/io.rs | 248 +++++++++++++++++++--------
rust/kernel/io/mem.rs | 16 +-
rust/kernel/io/poll.rs | 4 +-
rust/kernel/pci.rs | 10 +-
samples/rust/rust_driver_pci.rs | 2 +-
8 files changed, 255 insertions(+), 128 deletions(-)
diff --git a/drivers/gpu/nova-core/regs/macros.rs b/drivers/gpu/nova-core/regs/macros.rs
index fd1a815fa57d..5033bc0929ab 100644
--- a/drivers/gpu/nova-core/regs/macros.rs
+++ b/drivers/gpu/nova-core/regs/macros.rs
@@ -369,16 +369,18 @@ impl $name {
/// Read the register from its address in `io`.
#[inline(always)]
- pub(crate) fn read<const SIZE: usize, T>(io: &T) -> Self where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ pub(crate) fn read<T, I>(io: &T) -> Self where
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
{
Self(io.read32($offset))
}
/// Write the value contained in `self` to the register address in `io`.
#[inline(always)]
- pub(crate) fn write<const SIZE: usize, T>(self, io: &T) where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ pub(crate) fn write<T, I>(self, io: &T) where
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
{
io.write32(self.0, $offset)
}
@@ -386,11 +388,12 @@ pub(crate) fn write<const SIZE: usize, T>(self, io: &T) where
/// Read the register from its address in `io` and run `f` on its value to obtain a new
/// value to write back.
#[inline(always)]
- pub(crate) fn update<const SIZE: usize, T, F>(
+ pub(crate) fn update<T, I, F>(
io: &T,
f: F,
) where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
F: ::core::ops::FnOnce(Self) -> Self,
{
let reg = f(Self::read(io));
@@ -408,12 +411,13 @@ impl $name {
/// Read the register from `io`, using the base address provided by `base` and adding
/// the register's offset to it.
#[inline(always)]
- pub(crate) fn read<const SIZE: usize, T, B>(
+ pub(crate) fn read<T, I, B>(
io: &T,
#[allow(unused_variables)]
base: &B,
) -> Self where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
{
const OFFSET: usize = $name::OFFSET;
@@ -428,13 +432,14 @@ pub(crate) fn read<const SIZE: usize, T, B>(
/// Write the value contained in `self` to `io`, using the base address provided by
/// `base` and adding the register's offset to it.
#[inline(always)]
- pub(crate) fn write<const SIZE: usize, T, B>(
+ pub(crate) fn write<T, I, B>(
self,
io: &T,
#[allow(unused_variables)]
base: &B,
) where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
{
const OFFSET: usize = $name::OFFSET;
@@ -449,12 +454,13 @@ pub(crate) fn write<const SIZE: usize, T, B>(
/// the register's offset to it, then run `f` on its value to obtain a new value to
/// write back.
#[inline(always)]
- pub(crate) fn update<const SIZE: usize, T, B, F>(
+ pub(crate) fn update<T, I, B, F>(
io: &T,
base: &B,
f: F,
) where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
F: ::core::ops::FnOnce(Self) -> Self,
{
@@ -474,11 +480,12 @@ impl $name {
/// Read the array register at index `idx` from its address in `io`.
#[inline(always)]
- pub(crate) fn read<const SIZE: usize, T>(
+ pub(crate) fn read<T, I>(
io: &T,
idx: usize,
) -> Self where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
{
build_assert!(idx < Self::SIZE);
@@ -490,12 +497,13 @@ pub(crate) fn read<const SIZE: usize, T>(
/// Write the value contained in `self` to the array register with index `idx` in `io`.
#[inline(always)]
- pub(crate) fn write<const SIZE: usize, T>(
+ pub(crate) fn write<T, I>(
self,
io: &T,
idx: usize
) where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
{
build_assert!(idx < Self::SIZE);
@@ -507,12 +515,13 @@ pub(crate) fn write<const SIZE: usize, T>(
/// Read the array register at index `idx` in `io` and run `f` on its value to obtain a
/// new value to write back.
#[inline(always)]
- pub(crate) fn update<const SIZE: usize, T, F>(
+ pub(crate) fn update<T, I, F>(
io: &T,
idx: usize,
f: F,
) where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
F: ::core::ops::FnOnce(Self) -> Self,
{
let reg = f(Self::read(io, idx));
@@ -524,11 +533,12 @@ pub(crate) fn update<const SIZE: usize, T, F>(
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
- pub(crate) fn try_read<const SIZE: usize, T>(
+ pub(crate) fn try_read<T, I>(
io: &T,
idx: usize,
) -> ::kernel::error::Result<Self> where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
{
if idx < Self::SIZE {
Ok(Self::read(io, idx))
@@ -542,12 +552,13 @@ pub(crate) fn try_read<const SIZE: usize, T>(
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
- pub(crate) fn try_write<const SIZE: usize, T>(
+ pub(crate) fn try_write<T, I>(
self,
io: &T,
idx: usize,
) -> ::kernel::error::Result where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
{
if idx < Self::SIZE {
Ok(self.write(io, idx))
@@ -562,12 +573,13 @@ pub(crate) fn try_write<const SIZE: usize, T>(
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
- pub(crate) fn try_update<const SIZE: usize, T, F>(
+ pub(crate) fn try_update<T, I, F>(
io: &T,
idx: usize,
f: F,
) -> ::kernel::error::Result where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
F: ::core::ops::FnOnce(Self) -> Self,
{
if idx < Self::SIZE {
@@ -593,13 +605,14 @@ impl $name {
/// Read the array register at index `idx` from `io`, using the base address provided
/// by `base` and adding the register's offset to it.
#[inline(always)]
- pub(crate) fn read<const SIZE: usize, T, B>(
+ pub(crate) fn read<T, I, B>(
io: &T,
#[allow(unused_variables)]
base: &B,
idx: usize,
) -> Self where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
{
build_assert!(idx < Self::SIZE);
@@ -614,14 +627,15 @@ pub(crate) fn read<const SIZE: usize, T, B>(
/// Write the value contained in `self` to `io`, using the base address provided by
/// `base` and adding the offset of array register `idx` to it.
#[inline(always)]
- pub(crate) fn write<const SIZE: usize, T, B>(
+ pub(crate) fn write<T, I, B>(
self,
io: &T,
#[allow(unused_variables)]
base: &B,
idx: usize
) where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
{
build_assert!(idx < Self::SIZE);
@@ -636,13 +650,14 @@ pub(crate) fn write<const SIZE: usize, T, B>(
/// by `base` and adding the register's offset to it, then run `f` on its value to
/// obtain a new value to write back.
#[inline(always)]
- pub(crate) fn update<const SIZE: usize, T, B, F>(
+ pub(crate) fn update<T, I, B, F>(
io: &T,
base: &B,
idx: usize,
f: F,
) where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
F: ::core::ops::FnOnce(Self) -> Self,
{
@@ -656,12 +671,13 @@ pub(crate) fn update<const SIZE: usize, T, B, F>(
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
- pub(crate) fn try_read<const SIZE: usize, T, B>(
+ pub(crate) fn try_read<T, I, B>(
io: &T,
base: &B,
idx: usize,
) -> ::kernel::error::Result<Self> where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
{
if idx < Self::SIZE {
@@ -677,13 +693,14 @@ pub(crate) fn try_read<const SIZE: usize, T, B>(
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
- pub(crate) fn try_write<const SIZE: usize, T, B>(
+ pub(crate) fn try_write<T, I, B>(
self,
io: &T,
base: &B,
idx: usize,
) -> ::kernel::error::Result where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
{
if idx < Self::SIZE {
@@ -700,13 +717,14 @@ pub(crate) fn try_write<const SIZE: usize, T, B>(
/// The validity of `idx` is checked at run-time, and `EINVAL` is returned is the
/// access was out-of-bounds.
#[inline(always)]
- pub(crate) fn try_update<const SIZE: usize, T, B, F>(
+ pub(crate) fn try_update<T, I, B, F>(
io: &T,
base: &B,
idx: usize,
f: F,
) -> ::kernel::error::Result where
- T: ::core::ops::Deref<Target = ::kernel::io::Io<SIZE>>,
+ T: ::core::ops::Deref<Target = I>,
+ I: ::kernel::io::Io,
B: crate::regs::macros::RegisterBase<$base>,
F: ::core::ops::FnOnce(Self) -> Self,
{
diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios.rs
index 74ed6d61e6cc..cafb2d99c82b 100644
--- a/drivers/gpu/nova-core/vbios.rs
+++ b/drivers/gpu/nova-core/vbios.rs
@@ -10,6 +10,7 @@
use kernel::error::Result;
use kernel::prelude::*;
use kernel::ptr::{Alignable, Alignment};
+use kernel::io::Io;
use kernel::types::ARef;
/// The offset of the VBIOS ROM in the BAR0 space.
diff --git a/rust/kernel/devres.rs b/rust/kernel/devres.rs
index 10a6a1789854..12a4474df3c3 100644
--- a/rust/kernel/devres.rs
+++ b/rust/kernel/devres.rs
@@ -52,11 +52,11 @@ struct Inner<T: Send> {
/// # Examples
///
/// ```no_run
-/// # use kernel::{bindings, device::{Bound, Device}, devres::Devres, io::{Io, IoRaw}};
+/// # use kernel::{bindings, device::{Bound, Device}, devres::Devres, io::{Io, Mmio, MmioRaw}};
/// # use core::ops::Deref;
///
/// // See also [`pci::Bar`] for a real example.
-/// struct IoMem<const SIZE: usize>(IoRaw<SIZE>);
+/// struct IoMem<const SIZE: usize>(MmioRaw<SIZE>);
///
/// impl<const SIZE: usize> IoMem<SIZE> {
/// /// # Safety
@@ -71,7 +71,7 @@ struct Inner<T: Send> {
/// return Err(ENOMEM);
/// }
///
-/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?))
+/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?))
/// }
/// }
///
@@ -83,11 +83,11 @@ struct Inner<T: Send> {
/// }
///
/// impl<const SIZE: usize> Deref for IoMem<SIZE> {
-/// type Target = Io<SIZE>;
+/// type Target = Mmio<SIZE>;
///
/// fn deref(&self) -> &Self::Target {
/// // SAFETY: The memory range stored in `self` has been properly mapped in `Self::new`.
-/// unsafe { Io::from_raw(&self.0) }
+/// unsafe { Mmio::from_raw(&self.0) }
/// }
/// }
/// # fn no_run(dev: &Device<Bound>) -> Result<(), Error> {
@@ -230,7 +230,7 @@ pub fn device(&self) -> &Device {
///
/// ```no_run
/// # #![cfg(CONFIG_PCI)]
- /// # use kernel::{device::Core, devres::Devres, pci};
+ /// # use kernel::{device::Core, devres::Devres, io::Io, pci};
///
/// fn from_core(dev: &pci::Device<Core>, devres: Devres<pci::Bar<0x4>>) -> Result {
/// let bar = devres.access(dev.as_ref())?;
diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs
index ee182b0b5452..0b1e79075c99 100644
--- a/rust/kernel/io.rs
+++ b/rust/kernel/io.rs
@@ -18,16 +18,16 @@
/// By itself, the existence of an instance of this structure does not provide any guarantees that
/// the represented MMIO region does exist or is properly mapped.
///
-/// Instead, the bus specific MMIO implementation must convert this raw representation into an `Io`
-/// instance providing the actual memory accessors. Only by the conversion into an `Io` structure
-/// any guarantees are given.
-pub struct IoRaw<const SIZE: usize = 0> {
+/// Instead, the bus specific MMIO implementation must convert this raw representation into an
+/// `Mmio` instance providing the actual memory accessors. Only by the conversion into an `Mmio`
+/// structure any guarantees are given.
+pub struct MmioRaw<const SIZE: usize = 0> {
addr: usize,
maxsize: usize,
}
-impl<const SIZE: usize> IoRaw<SIZE> {
- /// Returns a new `IoRaw` instance on success, an error otherwise.
+impl<const SIZE: usize> MmioRaw<SIZE> {
+ /// Returns a new `MmioRaw` instance on success, an error otherwise.
pub fn new(addr: usize, maxsize: usize) -> Result<Self> {
if maxsize < SIZE {
return Err(EINVAL);
@@ -62,11 +62,11 @@ pub fn maxsize(&self) -> usize {
/// # Examples
///
/// ```no_run
-/// # use kernel::{bindings, ffi::c_void, io::{Io, IoRaw}};
+/// # use kernel::{bindings, ffi::c_void, io::{Io, Mmio, MmioRaw}};
/// # use core::ops::Deref;
///
/// // See also [`pci::Bar`] for a real example.
-/// struct IoMem<const SIZE: usize>(IoRaw<SIZE>);
+/// struct IoMem<const SIZE: usize>(MmioRaw<SIZE>);
///
/// impl<const SIZE: usize> IoMem<SIZE> {
/// /// # Safety
@@ -81,7 +81,7 @@ pub fn maxsize(&self) -> usize {
/// return Err(ENOMEM);
/// }
///
-/// Ok(IoMem(IoRaw::new(addr as usize, SIZE)?))
+/// Ok(IoMem(MmioRaw::new(addr as usize, SIZE)?))
/// }
/// }
///
@@ -93,11 +93,11 @@ pub fn maxsize(&self) -> usize {
/// }
///
/// impl<const SIZE: usize> Deref for IoMem<SIZE> {
-/// type Target = Io<SIZE>;
+/// type Target = Mmio<SIZE>;
///
/// fn deref(&self) -> &Self::Target {
/// // SAFETY: The memory range stored in `self` has been properly mapped in `Self::new`.
-/// unsafe { Io::from_raw(&self.0) }
+/// unsafe { Mmio::from_raw(&self.0) }
/// }
/// }
///
@@ -111,29 +111,31 @@ pub fn maxsize(&self) -> usize {
/// # }
/// ```
#[repr(transparent)]
-pub struct Io<const SIZE: usize = 0>(IoRaw<SIZE>);
+pub struct Mmio<const SIZE: usize = 0>(MmioRaw<SIZE>);
macro_rules! define_read {
- ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident -> $type_name:ty) => {
+ (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident -> $type_name:ty) => {
/// Read IO data from a given offset known at compile time.
///
/// Bound checks are performed on compile time, hence if the offset is not known at compile
/// time, the build will fail.
$(#[$attr])*
#[inline]
- pub fn $name(&self, offset: usize) -> $type_name {
+ $vis fn $name(&self, offset: usize) -> $type_name {
let addr = self.io_addr_assert::<$type_name>(offset);
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
unsafe { bindings::$c_fn(addr as *const c_void) }
}
+ };
+ (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident -> $type_name:ty) => {
/// Read IO data from a given offset.
///
/// Bound checks are performed on runtime, it fails if the offset (plus the type size) is
/// out of bounds.
$(#[$attr])*
- pub fn $try_name(&self, offset: usize) -> Result<$type_name> {
+ $vis fn $try_name(&self, offset: usize) -> Result<$type_name> {
let addr = self.io_addr::<$type_name>(offset)?;
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
@@ -143,26 +145,28 @@ pub fn $try_name(&self, offset: usize) -> Result<$type_name> {
}
macro_rules! define_write {
- ($(#[$attr:meta])* $name:ident, $try_name:ident, $c_fn:ident <- $type_name:ty) => {
+ (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident <- $type_name:ty) => {
/// Write IO data from a given offset known at compile time.
///
/// Bound checks are performed on compile time, hence if the offset is not known at compile
/// time, the build will fail.
$(#[$attr])*
#[inline]
- pub fn $name(&self, value: $type_name, offset: usize) {
+ $vis fn $name(&self, value: $type_name, offset: usize) {
let addr = self.io_addr_assert::<$type_name>(offset);
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
unsafe { bindings::$c_fn(value, addr as *mut c_void) }
}
+ };
+ (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident <- $type_name:ty) => {
/// Write IO data from a given offset.
///
/// Bound checks are performed on runtime, it fails if the offset (plus the type size) is
/// out of bounds.
$(#[$attr])*
- pub fn $try_name(&self, value: $type_name, offset: usize) -> Result {
+ $vis fn $try_name(&self, value: $type_name, offset: usize) -> Result {
let addr = self.io_addr::<$type_name>(offset)?;
// SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
@@ -172,43 +176,40 @@ pub fn $try_name(&self, value: $type_name, offset: usize) -> Result {
};
}
-impl<const SIZE: usize> Io<SIZE> {
- /// Converts an `IoRaw` into an `Io` instance, providing the accessors to the MMIO mapping.
- ///
- /// # Safety
- ///
- /// Callers must ensure that `addr` is the start of a valid I/O mapped memory region of size
- /// `maxsize`.
- pub unsafe fn from_raw(raw: &IoRaw<SIZE>) -> &Self {
- // SAFETY: `Io` is a transparent wrapper around `IoRaw`.
- unsafe { &*core::ptr::from_ref(raw).cast() }
+/// Checks whether an access of type `U` at the given `offset`
+/// is valid within this region.
+#[inline]
+const fn offset_valid<U>(offset: usize, size: usize) -> bool {
+ let type_size = core::mem::size_of::<U>();
+ if let Some(end) = offset.checked_add(type_size) {
+ end <= size && offset % type_size == 0
+ } else {
+ false
}
+}
+
+/// Represents a region of I/O space of a fixed size.
+///
+/// Provides common helpers for offset validation and address
+/// calculation on top of a base address and maximum size.
+///
+/// Types implementing this trait (e.g. MMIO BARs or PCI config
+/// regions) can share the same accessors.
+pub trait Io {
+ /// Minimum usable size
+ const MIN_SIZE: usize;
/// Returns the base address of this mapping.
- #[inline]
- pub fn addr(&self) -> usize {
- self.0.addr()
- }
+ fn addr(&self) -> usize;
/// Returns the maximum size of this mapping.
- #[inline]
- pub fn maxsize(&self) -> usize {
- self.0.maxsize()
- }
-
- #[inline]
- const fn offset_valid<U>(offset: usize, size: usize) -> bool {
- let type_size = core::mem::size_of::<U>();
- if let Some(end) = offset.checked_add(type_size) {
- end <= size && offset % type_size == 0
- } else {
- false
- }
- }
+ fn maxsize(&self) -> usize;
+ /// Returns the absolute I/O address for a given `offset`.
+ /// Performs runtime bounds checks using [`offset_valid`]
#[inline]
fn io_addr<U>(&self, offset: usize) -> Result<usize> {
- if !Self::offset_valid::<U>(offset, self.maxsize()) {
+ if !offset_valid::<U>(offset, self.maxsize()) {
return Err(EINVAL);
}
@@ -217,50 +218,157 @@ fn io_addr<U>(&self, offset: usize) -> Result<usize> {
self.addr().checked_add(offset).ok_or(EINVAL)
}
+ /// Returns the absolute I/O address for a given `offset`,
+ /// performing compile-time bound checks.
#[inline]
fn io_addr_assert<U>(&self, offset: usize) -> usize {
- build_assert!(Self::offset_valid::<U>(offset, SIZE));
+ build_assert!(offset_valid::<U>(offset, Self::MIN_SIZE));
self.addr() + offset
}
- define_read!(read8, try_read8, readb -> u8);
- define_read!(read16, try_read16, readw -> u16);
- define_read!(read32, try_read32, readl -> u32);
+ /// Infallible 8-bit read with compile-time bounds check.
+ fn read8(&self, offset: usize) -> u8;
+
+ /// Infallible 16-bit read with compile-time bounds check.
+ fn read16(&self, offset: usize) -> u16;
+
+ /// Infallible 32-bit read with compile-time bounds check.
+ fn read32(&self, offset: usize) -> u32;
+
+ /// Fallible 8-bit read with runtime bounds check.
+ fn try_read8(&self, offset: usize) -> Result<u8>;
+
+ /// Fallible 16-bit read with runtime bounds check.
+ fn try_read16(&self, offset: usize) -> Result<u16>;
+
+ /// Fallible 32-bit read with runtime bounds check.
+ fn try_read32(&self, offset: usize) -> Result<u32>;
+
+ /// Infallible 8-bit write with compile-time bounds check.
+ fn write8(&self, value: u8, offset: usize);
+
+ /// Infallible 16-bit write with compile-time bounds check.
+ fn write16(&self, value: u16, offset: usize);
+
+ /// Infallible 32-bit write with compile-time bounds check.
+ fn write32(&self, value: u32, offset: usize);
+
+ /// Fallible 8-bit write with runtime bounds check.
+ fn try_write8(&self, value: u8, offset: usize) -> Result;
+
+ /// Fallible 16-bit write with runtime bounds check.
+ fn try_write16(&self, value: u16, offset: usize) -> Result;
+
+ /// Fallible 32-bit write with runtime bounds check.
+ fn try_write32(&self, value: u32, offset: usize) -> Result;
+}
+
+/// Implement this trait if a backend supports 64-bit access.
+pub trait Io64: Io {
+ /// Infallible 64-bit read with compile-time bounds check (64-bit only).
+ fn read64(&self, offset: usize) -> u64;
+
+ /// Fallible 64-bit read with runtime bounds check (64-bit only).
+ fn try_read64(&self, offset: usize) -> Result<u64>;
+
+ /// Infallible 64-bit write with compile-time bounds check (64-bit only).
+ fn write64(&self, value: u64, offset: usize);
+
+ /// Fallible 64-bit write with runtime bounds check (64-bit only).
+ fn try_write64(&self, value: u64, offset: usize) -> Result;
+}
+
+impl<const SIZE: usize> Io for Mmio<SIZE> {
+ const MIN_SIZE: usize = SIZE;
+
+ /// Returns the base address of this mapping.
+ #[inline]
+ fn addr(&self) -> usize {
+ self.0.addr()
+ }
+
+ /// Returns the maximum size of this mapping.
+ #[inline]
+ fn maxsize(&self) -> usize {
+ self.0.maxsize()
+ }
+
+ define_read!(infallible, read8, readb -> u8);
+ define_read!(infallible, read16, readw -> u16);
+ define_read!(infallible, read32, readl -> u32);
+
+ define_read!(fallible, try_read8, readb -> u8);
+ define_read!(fallible, try_read16, readw -> u16);
+ define_read!(fallible, try_read32, readl -> u32);
+
+ define_write!(infallible, write8, writeb <- u8);
+ define_write!(infallible, write16, writew <- u16);
+ define_write!(infallible, write32, writel <- u32);
+
+ define_write!(fallible, try_write8, writeb <- u8);
+ define_write!(fallible, try_write16, writew <- u16);
+ define_write!(fallible, try_write32, writel <- u32);
+}
+
+#[cfg(CONFIG_64BIT)]
+impl<const SIZE: usize> Io64 for Mmio<SIZE> {
+ define_read!(infallible, read64, readq -> u64);
+ define_read!(fallible, try_read64, readq -> u64);
+
+ define_write!(infallible, write64, writeq <- u64);
+ define_write!(fallible, try_write64, writeq <- u64);
+}
+
+impl<const SIZE: usize> Mmio<SIZE> {
+ /// Converts an `MmioRaw` into an `Mmio` instance, providing the accessors to the MMIO mapping.
+ ///
+ /// # Safety
+ ///
+ /// Callers must ensure that `addr` is the start of a valid I/O mapped memory region of size
+ /// `maxsize`.
+ pub unsafe fn from_raw(raw: &MmioRaw<SIZE>) -> &Self {
+ // SAFETY: `Mmio` is a transparent wrapper around `MmioRaw`.
+ unsafe { &*core::ptr::from_ref(raw).cast() }
+ }
+
+ define_read!(infallible, pub read8_relaxed, readb_relaxed -> u8);
+ define_read!(infallible, pub read16_relaxed, readw_relaxed -> u16);
+ define_read!(infallible, pub read32_relaxed, readl_relaxed -> u32);
define_read!(
+ infallible,
#[cfg(CONFIG_64BIT)]
- read64,
- try_read64,
- readq -> u64
+ pub read64_relaxed,
+ readq_relaxed -> u64
);
- define_read!(read8_relaxed, try_read8_relaxed, readb_relaxed -> u8);
- define_read!(read16_relaxed, try_read16_relaxed, readw_relaxed -> u16);
- define_read!(read32_relaxed, try_read32_relaxed, readl_relaxed -> u32);
+ define_read!(fallible, pub try_read8_relaxed, readb_relaxed -> u8);
+ define_read!(fallible, pub try_read16_relaxed, readw_relaxed -> u16);
+ define_read!(fallible, pub try_read32_relaxed, readl_relaxed -> u32);
define_read!(
+ fallible,
#[cfg(CONFIG_64BIT)]
- read64_relaxed,
- try_read64_relaxed,
+ pub try_read64_relaxed,
readq_relaxed -> u64
);
- define_write!(write8, try_write8, writeb <- u8);
- define_write!(write16, try_write16, writew <- u16);
- define_write!(write32, try_write32, writel <- u32);
+ define_write!(infallible, pub write8_relaxed, writeb_relaxed <- u8);
+ define_write!(infallible, pub write16_relaxed, writew_relaxed <- u16);
+ define_write!(infallible, pub write32_relaxed, writel_relaxed <- u32);
define_write!(
+ infallible,
#[cfg(CONFIG_64BIT)]
- write64,
- try_write64,
- writeq <- u64
+ pub write64_relaxed,
+ writeq_relaxed <- u64
);
- define_write!(write8_relaxed, try_write8_relaxed, writeb_relaxed <- u8);
- define_write!(write16_relaxed, try_write16_relaxed, writew_relaxed <- u16);
- define_write!(write32_relaxed, try_write32_relaxed, writel_relaxed <- u32);
+ define_write!(fallible, pub try_write8_relaxed, writeb_relaxed <- u8);
+ define_write!(fallible, pub try_write16_relaxed, writew_relaxed <- u16);
+ define_write!(fallible, pub try_write32_relaxed, writel_relaxed <- u32);
define_write!(
+ fallible,
#[cfg(CONFIG_64BIT)]
- write64_relaxed,
- try_write64_relaxed,
+ pub try_write64_relaxed,
writeq_relaxed <- u64
);
}
diff --git a/rust/kernel/io/mem.rs b/rust/kernel/io/mem.rs
index 6f99510bfc3a..93cad8539b18 100644
--- a/rust/kernel/io/mem.rs
+++ b/rust/kernel/io/mem.rs
@@ -11,8 +11,8 @@
use crate::io;
use crate::io::resource::Region;
use crate::io::resource::Resource;
-use crate::io::Io;
-use crate::io::IoRaw;
+use crate::io::Mmio;
+use crate::io::MmioRaw;
use crate::prelude::*;
/// An IO request for a specific device and resource.
@@ -195,7 +195,7 @@ pub fn new<'a>(io_request: IoRequest<'a>) -> impl PinInit<Devres<Self>, Error> +
}
impl<const SIZE: usize> Deref for ExclusiveIoMem<SIZE> {
- type Target = Io<SIZE>;
+ type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
&self.iomem
@@ -209,10 +209,10 @@ fn deref(&self) -> &Self::Target {
///
/// # Invariants
///
-/// [`IoMem`] always holds an [`IoRaw`] instance that holds a valid pointer to the
+/// [`IoMem`] always holds an [`MmioRaw`] instance that holds a valid pointer to the
/// start of the I/O memory mapped region.
pub struct IoMem<const SIZE: usize = 0> {
- io: IoRaw<SIZE>,
+ io: MmioRaw<SIZE>,
}
impl<const SIZE: usize> IoMem<SIZE> {
@@ -247,7 +247,7 @@ fn ioremap(resource: &Resource) -> Result<Self> {
return Err(ENOMEM);
}
- let io = IoRaw::new(addr as usize, size)?;
+ let io = MmioRaw::new(addr as usize, size)?;
let io = IoMem { io };
Ok(io)
@@ -270,10 +270,10 @@ fn drop(&mut self) {
}
impl<const SIZE: usize> Deref for IoMem<SIZE> {
- type Target = Io<SIZE>;
+ type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
// SAFETY: Safe as by the invariant of `IoMem`.
- unsafe { Io::from_raw(&self.io) }
+ unsafe { Mmio::from_raw(&self.io) }
}
}
diff --git a/rust/kernel/io/poll.rs b/rust/kernel/io/poll.rs
index 613eb25047ef..a9fea091303b 100644
--- a/rust/kernel/io/poll.rs
+++ b/rust/kernel/io/poll.rs
@@ -37,12 +37,12 @@
/// # Examples
///
/// ```no_run
-/// use kernel::io::{Io, poll::read_poll_timeout};
+/// use kernel::io::{Io, Mmio, poll::read_poll_timeout};
/// use kernel::time::Delta;
///
/// const HW_READY: u16 = 0x01;
///
-/// fn wait_for_hardware<const SIZE: usize>(io: &Io<SIZE>) -> Result<()> {
+/// fn wait_for_hardware<const SIZE: usize>(io: &Mmio<SIZE>) -> Result<()> {
/// match read_poll_timeout(
/// // The `op` closure reads the value of a specific status register.
/// || io.try_read16(0x1000),
diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
index 7fcc5f6022c1..77a8eb39ad32 100644
--- a/rust/kernel/pci.rs
+++ b/rust/kernel/pci.rs
@@ -10,7 +10,7 @@
devres::Devres,
driver,
error::{from_result, to_result, Result},
- io::{Io, IoRaw},
+ io::{Mmio, MmioRaw},
irq::{self, IrqRequest},
str::CStr,
sync::aref::ARef,
@@ -313,7 +313,7 @@ pub struct Device<Ctx: device::DeviceContext = device::Normal>(
/// memory mapped PCI bar and its size.
pub struct Bar<const SIZE: usize = 0> {
pdev: ARef<Device>,
- io: IoRaw<SIZE>,
+ io: MmioRaw<SIZE>,
num: i32,
}
@@ -349,7 +349,7 @@ fn new(pdev: &Device, num: u32, name: &CStr) -> Result<Self> {
return Err(ENOMEM);
}
- let io = match IoRaw::new(ioptr, len as usize) {
+ let io = match MmioRaw::new(ioptr, len as usize) {
Ok(io) => io,
Err(err) => {
// SAFETY:
@@ -403,11 +403,11 @@ fn drop(&mut self) {
}
impl<const SIZE: usize> Deref for Bar<SIZE> {
- type Target = Io<SIZE>;
+ type Target = Mmio<SIZE>;
fn deref(&self) -> &Self::Target {
// SAFETY: By the type invariant of `Self`, the MMIO range in `self.io` is properly mapped.
- unsafe { Io::from_raw(&self.io) }
+ unsafe { Mmio::from_raw(&self.io) }
}
}
diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci.rs
index 55a683c39ed9..528e672b6b89 100644
--- a/samples/rust/rust_driver_pci.rs
+++ b/samples/rust/rust_driver_pci.rs
@@ -4,7 +4,7 @@
//!
//! To make this driver probe, QEMU must be run with `-device pci-testdev`.
-use kernel::{c_str, device::Core, devres::Devres, pci, prelude::*, sync::aref::ARef};
+use kernel::{c_str, device::Core, devres::Devres, io::Io, pci, prelude::*, sync::aref::ARef};
struct Regs;
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH RESEND v4 2/4] rust: io: factor out MMIO read/write macros
2025-11-04 14:27 [PATCH RESEND v4 0/4] rust: pci: add config space read/write support Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 1/4] rust: io: factor common I/O helpers into Io trait Zhi Wang
@ 2025-11-04 14:27 ` Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 3/4] rust: pci: add config space read/write support Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines Zhi Wang
3 siblings, 0 replies; 11+ messages in thread
From: Zhi Wang @ 2025-11-04 14:27 UTC (permalink / raw)
To: rust-for-linux, linux-pci, linux-kernel
Cc: dakr, aliceryhl, bhelgaas, kwilczynski, ojeda, alex.gaynor,
boqun.feng, gary, bjorn3_gh, lossin, a.hindborg, tmgross,
markus.probst, helgaas, cjia, smitra, ankita, aniketa, kwankhede,
targupta, acourbot, joelagnelf, jhubbard, zhiwang, Zhi Wang
Refactor the existing MMIO accessors to use common call macros
instead of inlining the bindings calls in each `define_{read,write}!`
expansion.
This factoring separates the common offset/bounds checks from the
low-level call pattern, making it easier to add additional I/O accessor
families.
No functional change intended.
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
rust/kernel/io.rs | 114 +++++++++++++++++++++++++++++-----------------
1 file changed, 73 insertions(+), 41 deletions(-)
diff --git a/rust/kernel/io.rs b/rust/kernel/io.rs
index 0b1e79075c99..2f4206166b86 100644
--- a/rust/kernel/io.rs
+++ b/rust/kernel/io.rs
@@ -113,8 +113,34 @@ pub fn maxsize(&self) -> usize {
#[repr(transparent)]
pub struct Mmio<const SIZE: usize = 0>(MmioRaw<SIZE>);
+macro_rules! call_mmio_read {
+ (infallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) => {
+ // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
+ unsafe { bindings::$c_fn($addr as *const c_void) as $type }
+ };
+
+ (fallible, $c_fn:ident, $self:ident, $type:ty, $addr:expr) => {{
+ // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
+ Ok(unsafe { bindings::$c_fn($addr as *const c_void) as $type })
+ }};
+}
+
+macro_rules! call_mmio_write {
+ (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {
+ // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
+ unsafe { bindings::$c_fn($value, $addr as *mut c_void) }
+ };
+
+ (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {{
+ // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
+ unsafe { bindings::$c_fn($value, $addr as *mut c_void) };
+ Ok(())
+ }};
+}
+
macro_rules! define_read {
- (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident -> $type_name:ty) => {
+ (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident, $c_fn:ident ->
+ $type_name:ty) => {
/// Read IO data from a given offset known at compile time.
///
/// Bound checks are performed on compile time, hence if the offset is not known at compile
@@ -124,12 +150,13 @@ macro_rules! define_read {
$vis fn $name(&self, offset: usize) -> $type_name {
let addr = self.io_addr_assert::<$type_name>(offset);
- // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
- unsafe { bindings::$c_fn(addr as *const c_void) }
+ // SAFETY: By the type invariant `addr` is a valid address for IO operations.
+ $call_macro!(infallible, $c_fn, self, $type_name, addr)
}
};
- (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident -> $type_name:ty) => {
+ (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ident, $c_fn:ident ->
+ $type_name:ty) => {
/// Read IO data from a given offset.
///
/// Bound checks are performed on runtime, it fails if the offset (plus the type size) is
@@ -138,14 +165,16 @@ macro_rules! define_read {
$vis fn $try_name(&self, offset: usize) -> Result<$type_name> {
let addr = self.io_addr::<$type_name>(offset)?;
- // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
- Ok(unsafe { bindings::$c_fn(addr as *const c_void) })
+ // SAFETY: By the type invariant `addr` is a valid address for IO operations.
+ $call_macro!(fallible, $c_fn, self, $type_name, addr)
}
};
}
+pub(crate) use define_read;
macro_rules! define_write {
- (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $c_fn:ident <- $type_name:ty) => {
+ (infallible, $(#[$attr:meta])* $vis:vis $name:ident, $call_macro:ident, $c_fn:ident <-
+ $type_name:ty) => {
/// Write IO data from a given offset known at compile time.
///
/// Bound checks are performed on compile time, hence if the offset is not known at compile
@@ -155,12 +184,12 @@ macro_rules! define_write {
$vis fn $name(&self, value: $type_name, offset: usize) {
let addr = self.io_addr_assert::<$type_name>(offset);
- // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
- unsafe { bindings::$c_fn(value, addr as *mut c_void) }
+ $call_macro!(infallible, $c_fn, self, $type_name, addr, value);
}
};
- (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $c_fn:ident <- $type_name:ty) => {
+ (fallible, $(#[$attr:meta])* $vis:vis $try_name:ident, $call_macro:ident, $c_fn:ident <-
+ $type_name:ty) => {
/// Write IO data from a given offset.
///
/// Bound checks are performed on runtime, it fails if the offset (plus the type size) is
@@ -169,12 +198,11 @@ macro_rules! define_write {
$vis fn $try_name(&self, value: $type_name, offset: usize) -> Result {
let addr = self.io_addr::<$type_name>(offset)?;
- // SAFETY: By the type invariant `addr` is a valid address for MMIO operations.
- unsafe { bindings::$c_fn(value, addr as *mut c_void) }
- Ok(())
+ $call_macro!(fallible, $c_fn, self, $type_name, addr, value)
}
};
}
+pub(crate) use define_write;
/// Checks whether an access of type `U` at the given `offset`
/// is valid within this region.
@@ -294,30 +322,30 @@ fn maxsize(&self) -> usize {
self.0.maxsize()
}
- define_read!(infallible, read8, readb -> u8);
- define_read!(infallible, read16, readw -> u16);
- define_read!(infallible, read32, readl -> u32);
+ define_read!(infallible, read8, call_mmio_read, readb -> u8);
+ define_read!(infallible, read16, call_mmio_read, readw -> u16);
+ define_read!(infallible, read32, call_mmio_read, readl -> u32);
- define_read!(fallible, try_read8, readb -> u8);
- define_read!(fallible, try_read16, readw -> u16);
- define_read!(fallible, try_read32, readl -> u32);
+ define_read!(fallible, try_read8, call_mmio_read, readb -> u8);
+ define_read!(fallible, try_read16, call_mmio_read, readw -> u16);
+ define_read!(fallible, try_read32, call_mmio_read, readl -> u32);
- define_write!(infallible, write8, writeb <- u8);
- define_write!(infallible, write16, writew <- u16);
- define_write!(infallible, write32, writel <- u32);
+ define_write!(infallible, write8, call_mmio_write, writeb <- u8);
+ define_write!(infallible, write16, call_mmio_write, writew <- u16);
+ define_write!(infallible, write32, call_mmio_write, writel <- u32);
- define_write!(fallible, try_write8, writeb <- u8);
- define_write!(fallible, try_write16, writew <- u16);
- define_write!(fallible, try_write32, writel <- u32);
+ define_write!(fallible, try_write8, call_mmio_write, writeb <- u8);
+ define_write!(fallible, try_write16, call_mmio_write, writew <- u16);
+ define_write!(fallible, try_write32, call_mmio_write, writel <- u32);
}
#[cfg(CONFIG_64BIT)]
impl<const SIZE: usize> Io64 for Mmio<SIZE> {
- define_read!(infallible, read64, readq -> u64);
- define_read!(fallible, try_read64, readq -> u64);
+ define_read!(infallible, read64, call_mmio_read, readq -> u64);
+ define_read!(fallible, try_read64, call_mmio_read, readq -> u64);
- define_write!(infallible, write64, writeq <- u64);
- define_write!(fallible, try_write64, writeq <- u64);
+ define_write!(infallible, write64, call_mmio_write, writeq <- u64);
+ define_write!(fallible, try_write64, call_mmio_write, writeq <- u64);
}
impl<const SIZE: usize> Mmio<SIZE> {
@@ -332,43 +360,47 @@ pub unsafe fn from_raw(raw: &MmioRaw<SIZE>) -> &Self {
unsafe { &*core::ptr::from_ref(raw).cast() }
}
- define_read!(infallible, pub read8_relaxed, readb_relaxed -> u8);
- define_read!(infallible, pub read16_relaxed, readw_relaxed -> u16);
- define_read!(infallible, pub read32_relaxed, readl_relaxed -> u32);
+ define_read!(infallible, pub read8_relaxed, call_mmio_read, readb_relaxed -> u8);
+ define_read!(infallible, pub read16_relaxed, call_mmio_read, readw_relaxed -> u16);
+ define_read!(infallible, pub read32_relaxed, call_mmio_read, readl_relaxed -> u32);
define_read!(
infallible,
#[cfg(CONFIG_64BIT)]
pub read64_relaxed,
+ call_mmio_read,
readq_relaxed -> u64
);
- define_read!(fallible, pub try_read8_relaxed, readb_relaxed -> u8);
- define_read!(fallible, pub try_read16_relaxed, readw_relaxed -> u16);
- define_read!(fallible, pub try_read32_relaxed, readl_relaxed -> u32);
+ define_read!(fallible, pub try_read8_relaxed, call_mmio_read, readb_relaxed -> u8);
+ define_read!(fallible, pub try_read16_relaxed, call_mmio_read, readw_relaxed -> u16);
+ define_read!(fallible, pub try_read32_relaxed, call_mmio_read, readl_relaxed -> u32);
define_read!(
fallible,
#[cfg(CONFIG_64BIT)]
pub try_read64_relaxed,
+ call_mmio_read,
readq_relaxed -> u64
);
- define_write!(infallible, pub write8_relaxed, writeb_relaxed <- u8);
- define_write!(infallible, pub write16_relaxed, writew_relaxed <- u16);
- define_write!(infallible, pub write32_relaxed, writel_relaxed <- u32);
+ define_write!(infallible, pub write8_relaxed, call_mmio_write, writeb_relaxed <- u8);
+ define_write!(infallible, pub write16_relaxed, call_mmio_write, writew_relaxed <- u16);
+ define_write!(infallible, pub write32_relaxed, call_mmio_write, writel_relaxed <- u32);
define_write!(
infallible,
#[cfg(CONFIG_64BIT)]
pub write64_relaxed,
+ call_mmio_write,
writeq_relaxed <- u64
);
- define_write!(fallible, pub try_write8_relaxed, writeb_relaxed <- u8);
- define_write!(fallible, pub try_write16_relaxed, writew_relaxed <- u16);
- define_write!(fallible, pub try_write32_relaxed, writel_relaxed <- u32);
+ define_write!(fallible, pub try_write8_relaxed, call_mmio_write, writeb_relaxed <- u8);
+ define_write!(fallible, pub try_write16_relaxed, call_mmio_write, writew_relaxed <- u16);
+ define_write!(fallible, pub try_write32_relaxed, call_mmio_write, writel_relaxed <- u32);
define_write!(
fallible,
#[cfg(CONFIG_64BIT)]
pub try_write64_relaxed,
+ call_mmio_write,
writeq_relaxed <- u64
);
}
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH RESEND v4 3/4] rust: pci: add config space read/write support
2025-11-04 14:27 [PATCH RESEND v4 0/4] rust: pci: add config space read/write support Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 1/4] rust: io: factor common I/O helpers into Io trait Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 2/4] rust: io: factor out MMIO read/write macros Zhi Wang
@ 2025-11-04 14:27 ` Zhi Wang
2025-11-04 15:36 ` Danilo Krummrich
2025-11-04 15:38 ` Danilo Krummrich
2025-11-04 14:27 ` [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines Zhi Wang
3 siblings, 2 replies; 11+ messages in thread
From: Zhi Wang @ 2025-11-04 14:27 UTC (permalink / raw)
To: rust-for-linux, linux-pci, linux-kernel
Cc: dakr, aliceryhl, bhelgaas, kwilczynski, ojeda, alex.gaynor,
boqun.feng, gary, bjorn3_gh, lossin, a.hindborg, tmgross,
markus.probst, helgaas, cjia, smitra, ankita, aniketa, kwankhede,
targupta, acourbot, joelagnelf, jhubbard, zhiwang, Zhi Wang
Drivers might need to access PCI config space for querying capability
structures and access the registers inside the structures.
For Rust drivers need to access PCI config space, the Rust PCI abstraction
needs to support it in a way that upholds Rust's safety principles.
Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe
accessors for PCI config space. The new type implements the `Io` trait to
share offset validation and bound-checking logic with others.
Cc: Danilo Krummrich <dakr@kernel.org>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
rust/kernel/pci.rs | 148 +++++++++++++++++++++++++++++++++++++++++++--
1 file changed, 142 insertions(+), 6 deletions(-)
diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
index 77a8eb39ad32..630660a7f05d 100644
--- a/rust/kernel/pci.rs
+++ b/rust/kernel/pci.rs
@@ -5,13 +5,31 @@
//! C header: [`include/linux/pci.h`](srctree/include/linux/pci.h)
use crate::{
- bindings, container_of, device,
- device_id::{RawDeviceId, RawDeviceIdIndex},
+ bindings,
+ container_of,
+ device,
+ device_id::{
+ RawDeviceId,
+ RawDeviceIdIndex
+ },
devres::Devres,
driver,
- error::{from_result, to_result, Result},
- io::{Mmio, MmioRaw},
- irq::{self, IrqRequest},
+ error::{
+ from_result,
+ to_result,
+ Result
+ },
+ io::{
+ define_read,
+ define_write,
+ Io,
+ Mmio,
+ MmioRaw
+ },
+ irq::{
+ self,
+ IrqRequest
+ },
str::CStr,
sync::aref::ARef,
types::Opaque,
@@ -20,7 +38,10 @@
use core::{
marker::PhantomData,
ops::Deref,
- ptr::{addr_of_mut, NonNull},
+ ptr::{
+ addr_of_mut,
+ NonNull
+ },
};
use kernel::prelude::*;
@@ -305,6 +326,83 @@ pub struct Device<Ctx: device::DeviceContext = device::Normal>(
PhantomData<Ctx>,
);
+/// Represents the PCI configuration space of a device.
+///
+/// Provides typed read and write accessors for configuration registers
+/// using the standard `pci_read_config_*` and `pci_write_config_*` helpers.
+///
+/// The generic const parameter `SIZE` can be used to indicate the
+/// maximum size of the configuration space (e.g. 256 bytes for legacy,
+/// 4096 bytes for extended config space). The actual size is obtained
+/// from the underlying `struct pci_dev` via [`Device::cfg_size`].
+pub struct ConfigSpace<'a, const SIZE: usize = { ConfigSpaceSize::Extended as usize }> {
+ pdev: &'a Device<device::Core>,
+}
+
+macro_rules! call_config_read {
+ (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) => {{
+ let mut val: $ty = 0;
+ let ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, &mut val) };
+ match ret {
+ 0 => val,
+ _ => !0,
+ }
+ }};
+
+ (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) => {{
+ let mut val: $ty = 0;
+ let ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, &mut val) };
+ (ret == 0)
+ .then_some(Ok(val))
+ .unwrap_or_else(|| Err(Error::from_errno(ret)))
+ }};
+}
+
+macro_rules! call_config_write {
+ (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {
+ let _ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, $value) };
+ };
+
+ (fallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr, $value:expr) => {{
+ let ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, $value) };
+ (ret == 0)
+ .then_some(Ok(()))
+ .unwrap_or_else(|| Err(Error::from_errno(ret)))
+ }};
+}
+
+impl<'a, const SIZE: usize> Io for ConfigSpace<'a, SIZE> {
+ const MIN_SIZE: usize = SIZE;
+
+ /// Returns the base address of this mapping.
+ #[inline]
+ fn addr(&self) -> usize {
+ 0
+ }
+
+ /// Returns the maximum size of this mapping.
+ #[inline]
+ fn maxsize(&self) -> usize {
+ self.pdev.cfg_size().map_or(0, |v| v as usize)
+ }
+
+ define_read!(infallible, read8, call_config_read, pci_read_config_byte -> u8);
+ define_read!(infallible, read16, call_config_read, pci_read_config_word -> u16);
+ define_read!(infallible, read32, call_config_read, pci_read_config_dword -> u32);
+
+ define_read!(fallible, try_read8, call_config_read, pci_read_config_byte -> u8);
+ define_read!(fallible, try_read16, call_config_read, pci_read_config_word -> u16);
+ define_read!(fallible, try_read32, call_config_read, pci_read_config_dword -> u32);
+
+ define_write!(infallible, write8, call_config_write, pci_write_config_byte <- u8);
+ define_write!(infallible, write16, call_config_write, pci_write_config_word <- u16);
+ define_write!(infallible, write32, call_config_write, pci_write_config_dword <- u32);
+
+ define_write!(fallible, try_write8, call_config_write, pci_write_config_byte <- u8);
+ define_write!(fallible, try_write16, call_config_write, pci_write_config_word <- u16);
+ define_write!(fallible, try_write32, call_config_write, pci_write_config_dword <- u32);
+}
+
/// A PCI BAR to perform I/O-Operations on.
///
/// # Invariants
@@ -418,6 +516,19 @@ fn as_raw(&self) -> *mut bindings::pci_dev {
}
}
+/// Represents the size of a PCI configuration space.
+///
+/// PCI devices can have either a *normal* (legacy) configuration space of 256 bytes,
+/// or an *extended* configuration space of 4096 bytes as defined in the PCI Express
+/// specification.
+pub enum ConfigSpaceSize {
+ /// 256-byte legacy PCI configuration space.
+ Normal = 256,
+
+ /// 4096-byte PCIe extended configuration space.
+ Extended = 4096,
+}
+
impl Device {
/// Returns the PCI vendor ID as [`Vendor`].
///
@@ -514,6 +625,17 @@ pub fn pci_class(&self) -> Class {
// SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
Class::from_raw(unsafe { (*self.as_raw()).class })
}
+
+ /// Returns the size of configuration space.
+ fn cfg_size(&self) -> Result<ConfigSpaceSize> {
+ // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
+ let size = unsafe { (*self.as_raw()).cfg_size };
+ match size {
+ 256 => Ok(ConfigSpaceSize::Normal),
+ 4096 => Ok(ConfigSpaceSize::Extended),
+ _ => Err(EINVAL),
+ }
+ }
}
impl Device<device::Bound> {
@@ -591,6 +713,20 @@ pub fn set_master(&self) {
// SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid `struct pci_dev`.
unsafe { bindings::pci_set_master(self.as_raw()) };
}
+
+ /// Return an initialized config space object.
+ pub fn config_space<'a>(
+ &'a self,
+ ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Normal as usize }>> {
+ Ok(ConfigSpace { pdev: self })
+ }
+
+ /// Return an initialized config space object.
+ pub fn config_space_exteneded<'a>(
+ &'a self,
+ ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Extended as usize }>> {
+ Ok(ConfigSpace { pdev: self })
+ }
}
// SAFETY: `Device` is a transparent wrapper of a type that doesn't depend on `Device`'s generic
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines
2025-11-04 14:27 [PATCH RESEND v4 0/4] rust: pci: add config space read/write support Zhi Wang
` (2 preceding siblings ...)
2025-11-04 14:27 ` [PATCH RESEND v4 3/4] rust: pci: add config space read/write support Zhi Wang
@ 2025-11-04 14:27 ` Zhi Wang
2025-11-04 15:41 ` Danilo Krummrich
3 siblings, 1 reply; 11+ messages in thread
From: Zhi Wang @ 2025-11-04 14:27 UTC (permalink / raw)
To: rust-for-linux, linux-pci, linux-kernel
Cc: dakr, aliceryhl, bhelgaas, kwilczynski, ojeda, alex.gaynor,
boqun.feng, gary, bjorn3_gh, lossin, a.hindborg, tmgross,
markus.probst, helgaas, cjia, smitra, ankita, aniketa, kwankhede,
targupta, acourbot, joelagnelf, jhubbard, zhiwang, Zhi Wang
Add tests exercising the PCI configuration space helpers.
Suggested-by: Danilo Krummrich <dakr@kernel.org>
Signed-off-by: Zhi Wang <zhiw@nvidia.com>
---
samples/rust/rust_driver_pci.rs | 46 +++++++++++++++++++++++++++++++++
1 file changed, 46 insertions(+)
diff --git a/samples/rust/rust_driver_pci.rs b/samples/rust/rust_driver_pci.rs
index 528e672b6b89..6f0324b6bdf6 100644
--- a/samples/rust/rust_driver_pci.rs
+++ b/samples/rust/rust_driver_pci.rs
@@ -58,6 +58,50 @@ fn testdev(index: &TestIndex, bar: &Bar0) -> Result<u32> {
Ok(bar.read32(Regs::COUNT))
}
+
+ fn config_space(pdev: &pci::Device<Core>) -> Result {
+ let config = pdev.config_space()?;
+
+ // TODO: use the register!() macro for defining PCI configuration space registers once it
+ // has been move out of nova-core.
+ dev_info!(
+ pdev.as_ref(),
+ "pci-testdev config space read8 rev ID: {:x}\n",
+ config.read8(0x8)
+ );
+
+ dev_info!(
+ pdev.as_ref(),
+ "pci-testdev config space read16 vendor ID: {:x}\n",
+ config.read16(0)
+ );
+
+ dev_info!(
+ pdev.as_ref(),
+ "pci-testdev config space read32 BAR 0: {:x}\n",
+ config.read32(0x10)
+ );
+
+ dev_info!(
+ pdev.as_ref(),
+ "pci-testdev config space try_read8 rev ID: {:x}\n",
+ config.try_read8(0x8)?
+ );
+
+ dev_info!(
+ pdev.as_ref(),
+ "pci-testdev config space try_read16 vendor ID: {:x}\n",
+ config.try_read16(0)?
+ );
+
+ dev_info!(
+ pdev.as_ref(),
+ "pci-testdev config space try_read32 BAR 0: {:x}\n",
+ config.try_read32(0x10)?
+ );
+
+ Ok(())
+ }
}
impl pci::Driver for SampleDriver {
@@ -93,6 +137,8 @@ fn probe(pdev: &pci::Device<Core>, info: &Self::IdInfo) -> Result<Pin<KBox<Self>
Self::testdev(info, bar)?
);
+ Self::config_space(pdev)?;
+
Ok(drvdata)
}
--
2.51.0
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH RESEND v4 3/4] rust: pci: add config space read/write support
2025-11-04 14:27 ` [PATCH RESEND v4 3/4] rust: pci: add config space read/write support Zhi Wang
@ 2025-11-04 15:36 ` Danilo Krummrich
2025-11-04 16:19 ` Zhi Wang
2025-11-04 15:38 ` Danilo Krummrich
1 sibling, 1 reply; 11+ messages in thread
From: Danilo Krummrich @ 2025-11-04 15:36 UTC (permalink / raw)
To: Zhi Wang
Cc: rust-for-linux, linux-pci, linux-kernel, aliceryhl, bhelgaas,
kwilczynski, ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh,
lossin, a.hindborg, tmgross, markus.probst, helgaas, cjia, smitra,
ankita, aniketa, kwankhede, targupta, acourbot, joelagnelf,
jhubbard, zhiwang
On Tue Nov 4, 2025 at 3:27 PM CET, Zhi Wang wrote:
> Drivers might need to access PCI config space for querying capability
> structures and access the registers inside the structures.
>
> For Rust drivers need to access PCI config space, the Rust PCI abstraction
> needs to support it in a way that upholds Rust's safety principles.
>
> Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to provide safe
> accessors for PCI config space. The new type implements the `Io` trait to
> share offset validation and bound-checking logic with others.
>
> Cc: Danilo Krummrich <dakr@kernel.org>
> Signed-off-by: Zhi Wang <zhiw@nvidia.com>
> ---
> rust/kernel/pci.rs | 148 +++++++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 142 insertions(+), 6 deletions(-)
>
> diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
> index 77a8eb39ad32..630660a7f05d 100644
> --- a/rust/kernel/pci.rs
> +++ b/rust/kernel/pci.rs
> @@ -5,13 +5,31 @@
> //! C header: [`include/linux/pci.h`](srctree/include/linux/pci.h)
>
> use crate::{
> - bindings, container_of, device,
> - device_id::{RawDeviceId, RawDeviceIdIndex},
> + bindings,
> + container_of,
> + device,
> + device_id::{
> + RawDeviceId,
> + RawDeviceIdIndex
> + },
> devres::Devres,
> driver,
> - error::{from_result, to_result, Result},
> - io::{Mmio, MmioRaw},
> - irq::{self, IrqRequest},
> + error::{
> + from_result,
> + to_result,
> + Result
> + },
> + io::{
> + define_read,
> + define_write,
> + Io,
> + Mmio,
> + MmioRaw
> + },
> + irq::{
> + self,
> + IrqRequest
> + },
> str::CStr,
> sync::aref::ARef,
> types::Opaque,
> @@ -20,7 +38,10 @@
> use core::{
> marker::PhantomData,
> ops::Deref,
> - ptr::{addr_of_mut, NonNull},
> + ptr::{
> + addr_of_mut,
> + NonNull
> + },
> };
Please add a comma and use `//` at the end of the last element of a block as
described in [1]. Otherwise rustfmt will change it up again.
I think most of the diff is not related to this patch. I think it would be good
to convert the whole module and then add further changes.
I just did such a cleanup for the I/O module [1], I can send another patch for
all the PCI stuff.
[1] https://docs.kernel.org/rust/coding-guidelines.html#imports
[2] https://lore.kernel.org/lkml/20251104133301.59402-1-dakr@kernel.org/
> use kernel::prelude::*;
>
> @@ -305,6 +326,83 @@ pub struct Device<Ctx: device::DeviceContext = device::Normal>(
> PhantomData<Ctx>,
> );
>
> +/// Represents the PCI configuration space of a device.
> +///
> +/// Provides typed read and write accessors for configuration registers
> +/// using the standard `pci_read_config_*` and `pci_write_config_*` helpers.
> +///
> +/// The generic const parameter `SIZE` can be used to indicate the
> +/// maximum size of the configuration space (e.g. 256 bytes for legacy,
> +/// 4096 bytes for extended config space). The actual size is obtained
> +/// from the underlying `struct pci_dev` via [`Device::cfg_size`].
> +pub struct ConfigSpace<'a, const SIZE: usize = { ConfigSpaceSize::Extended as usize }> {
> + pdev: &'a Device<device::Core>,
> +}
> +
> +macro_rules! call_config_read {
> + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) => {{
> + let mut val: $ty = 0;
> + let ret = unsafe { bindings::$c_fn($self.pdev.as_raw(), $addr as i32, &mut val) };
> + match ret {
> + 0 => val,
> + _ => !0,
> + }
I think the match is not needed, the value should already be set accordingly.
> + }};
> +/// Represents the size of a PCI configuration space.
> +///
> +/// PCI devices can have either a *normal* (legacy) configuration space of 256 bytes,
> +/// or an *extended* configuration space of 4096 bytes as defined in the PCI Express
> +/// specification.
> +pub enum ConfigSpaceSize {
I think this should be [repr(usize)].
> + /// 256-byte legacy PCI configuration space.
> + Normal = 256,
> +
> + /// 4096-byte PCIe extended configuration space.
> + Extended = 4096,
> +}
> +
> impl Device {
> /// Returns the PCI vendor ID as [`Vendor`].
> ///
> @@ -514,6 +625,17 @@ pub fn pci_class(&self) -> Class {
> // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
> Class::from_raw(unsafe { (*self.as_raw()).class })
> }
> +
> + /// Returns the size of configuration space.
> + fn cfg_size(&self) -> Result<ConfigSpaceSize> {
> + // SAFETY: `self.as_raw` is a valid pointer to a `struct pci_dev`.
> + let size = unsafe { (*self.as_raw()).cfg_size };
> + match size {
> + 256 => Ok(ConfigSpaceSize::Normal),
> + 4096 => Ok(ConfigSpaceSize::Extended),
> + _ => Err(EINVAL),
I'd add a debug_assert!() in this case.
> + }
> + }
> }
>
> impl Device<device::Bound> {
> @@ -591,6 +713,20 @@ pub fn set_master(&self) {
> // SAFETY: `self.as_raw` is guaranteed to be a pointer to a valid `struct pci_dev`.
> unsafe { bindings::pci_set_master(self.as_raw()) };
> }
> +
> + /// Return an initialized config space object.
> + pub fn config_space<'a>(
> + &'a self,
> + ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Normal as usize }>> {
Let's add as_raw() to ConfigSpaceSize and use that instead.
> + Ok(ConfigSpace { pdev: self })
> + }
> +
> + /// Return an initialized config space object.
> + pub fn config_space_exteneded<'a>(
> + &'a self,
> + ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Extended as usize }>> {
> + Ok(ConfigSpace { pdev: self })
> + }
> }
>
> // SAFETY: `Device` is a transparent wrapper of a type that doesn't depend on `Device`'s generic
> --
> 2.51.0
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RESEND v4 3/4] rust: pci: add config space read/write support
2025-11-04 14:27 ` [PATCH RESEND v4 3/4] rust: pci: add config space read/write support Zhi Wang
2025-11-04 15:36 ` Danilo Krummrich
@ 2025-11-04 15:38 ` Danilo Krummrich
1 sibling, 0 replies; 11+ messages in thread
From: Danilo Krummrich @ 2025-11-04 15:38 UTC (permalink / raw)
To: Zhi Wang
Cc: rust-for-linux, linux-pci, linux-kernel, aliceryhl, bhelgaas,
kwilczynski, ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh,
lossin, a.hindborg, tmgross, markus.probst, helgaas, cjia, smitra,
ankita, aniketa, kwankhede, targupta, acourbot, joelagnelf,
jhubbard, zhiwang
On Tue Nov 4, 2025 at 3:27 PM CET, Zhi Wang wrote:
> +/// Represents the PCI configuration space of a device.
> +///
> +/// Provides typed read and write accessors for configuration registers
> +/// using the standard `pci_read_config_*` and `pci_write_config_*` helpers.
> +///
> +/// The generic const parameter `SIZE` can be used to indicate the
> +/// maximum size of the configuration space (e.g. 256 bytes for legacy,
> +/// 4096 bytes for extended config space). The actual size is obtained
> +/// from the underlying `struct pci_dev` via [`Device::cfg_size`].
> +pub struct ConfigSpace<'a, const SIZE: usize = { ConfigSpaceSize::Extended as usize }> {
> + pdev: &'a Device<device::Core>,
> +}
Device<Bound> should be enough, we don't need to require the core context.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines
2025-11-04 14:27 ` [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines Zhi Wang
@ 2025-11-04 15:41 ` Danilo Krummrich
2025-11-04 16:42 ` Zhi Wang
0 siblings, 1 reply; 11+ messages in thread
From: Danilo Krummrich @ 2025-11-04 15:41 UTC (permalink / raw)
To: Zhi Wang
Cc: rust-for-linux, linux-pci, linux-kernel, aliceryhl, bhelgaas,
kwilczynski, ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh,
lossin, a.hindborg, tmgross, markus.probst, helgaas, cjia, smitra,
ankita, aniketa, kwankhede, targupta, acourbot, joelagnelf,
jhubbard, zhiwang
On Tue Nov 4, 2025 at 3:27 PM CET, Zhi Wang wrote:
> + fn config_space(pdev: &pci::Device<Core>) -> Result {
> + let config = pdev.config_space()?;
> +
> + // TODO: use the register!() macro for defining PCI configuration space registers once it
> + // has been move out of nova-core.
> + dev_info!(
> + pdev.as_ref(),
> + "pci-testdev config space read8 rev ID: {:x}\n",
> + config.read8(0x8)
> + );
> +
> + dev_info!(
> + pdev.as_ref(),
> + "pci-testdev config space read16 vendor ID: {:x}\n",
> + config.read16(0)
> + );
> +
> + dev_info!(
> + pdev.as_ref(),
> + "pci-testdev config space read32 BAR 0: {:x}\n",
> + config.read32(0x10)
> + );
> +
> + dev_info!(
> + pdev.as_ref(),
> + "pci-testdev config space try_read8 rev ID: {:x}\n",
> + config.try_read8(0x8)?
> + );
> +
> + dev_info!(
> + pdev.as_ref(),
> + "pci-testdev config space try_read16 vendor ID: {:x}\n",
> + config.try_read16(0)?
> + );
> +
> + dev_info!(
> + pdev.as_ref(),
> + "pci-testdev config space try_read32 BAR 0: {:x}\n",
> + config.try_read32(0x10)?
> + );
If we want to demonstrate the fallible accessors we should try accesses outside
the bounds of the requested config space size. However, that doesn't really make
sense, because in this case the driver could have been calling
config_space_extended() instead.
So, I think the fallible versions don't really serve a purpose and we should
probably drop them.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RESEND v4 3/4] rust: pci: add config space read/write support
2025-11-04 15:36 ` Danilo Krummrich
@ 2025-11-04 16:19 ` Zhi Wang
0 siblings, 0 replies; 11+ messages in thread
From: Zhi Wang @ 2025-11-04 16:19 UTC (permalink / raw)
To: Danilo Krummrich
Cc: rust-for-linux, linux-pci, linux-kernel, aliceryhl, bhelgaas,
kwilczynski, ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh,
lossin, a.hindborg, tmgross, markus.probst, helgaas, cjia, smitra,
ankita, aniketa, kwankhede, targupta, acourbot, joelagnelf,
jhubbard, zhiwang
On Tue, 04 Nov 2025 16:36:35 +0100
"Danilo Krummrich" <dakr@kernel.org> wrote:
> On Tue Nov 4, 2025 at 3:27 PM CET, Zhi Wang wrote:
> > Drivers might need to access PCI config space for querying
> > capability structures and access the registers inside the
> > structures.
> >
> > For Rust drivers need to access PCI config space, the Rust PCI
> > abstraction needs to support it in a way that upholds Rust's safety
> > principles.
> >
> > Introduce a `ConfigSpace` wrapper in Rust PCI abstraction to
> > provide safe accessors for PCI config space. The new type
> > implements the `Io` trait to share offset validation and
> > bound-checking logic with others.
> >
> > Cc: Danilo Krummrich <dakr@kernel.org>
> > Signed-off-by: Zhi Wang <zhiw@nvidia.com>
> > ---
> > rust/kernel/pci.rs | 148
> > +++++++++++++++++++++++++++++++++++++++++++-- 1 file changed, 142
> > insertions(+), 6 deletions(-)
> >
> > diff --git a/rust/kernel/pci.rs b/rust/kernel/pci.rs
> > index 77a8eb39ad32..630660a7f05d 100644
> > --- a/rust/kernel/pci.rs
> > +++ b/rust/kernel/pci.rs
> > @@ -5,13 +5,31 @@
> > //! C header: [`include/linux/pci.h`](srctree/include/linux/pci.h)
> >
> > use crate::{
> > - bindings, container_of, device,
> > - device_id::{RawDeviceId, RawDeviceIdIndex},
> > + bindings,
> > + container_of,
> > + device,
> > + device_id::{
> > + RawDeviceId,
> > + RawDeviceIdIndex
> > + },
> > devres::Devres,
> > driver,
> > - error::{from_result, to_result, Result},
> > - io::{Mmio, MmioRaw},
> > - irq::{self, IrqRequest},
> > + error::{
> > + from_result,
> > + to_result,
> > + Result
> > + },
> > + io::{
> > + define_read,
> > + define_write,
> > + Io,
> > + Mmio,
> > + MmioRaw
> > + },
> > + irq::{
> > + self,
> > + IrqRequest
> > + },
> > str::CStr,
> > sync::aref::ARef,
> > types::Opaque,
> > @@ -20,7 +38,10 @@
> > use core::{
> > marker::PhantomData,
> > ops::Deref,
> > - ptr::{addr_of_mut, NonNull},
> > + ptr::{
> > + addr_of_mut,
> > + NonNull
> > + },
> > };
>
> Please add a comma and use `//` at the end of the last element of a
> block as described in [1]. Otherwise rustfmt will change it up again.
>
I see.
> I think most of the diff is not related to this patch. I think it
> would be good to convert the whole module and then add further
> changes.
>
> I just did such a cleanup for the I/O module [1], I can send another
> patch for all the PCI stuff.
>
I can rebase this series on top of yours once your sent them out.
> [1] https://docs.kernel.org/rust/coding-guidelines.html#imports
> [2]
> https://lore.kernel.org/lkml/20251104133301.59402-1-dakr@kernel.org/
>
> > use kernel::prelude::*;
> >
> > @@ -305,6 +326,83 @@ pub struct Device<Ctx: device::DeviceContext =
> > device::Normal>( PhantomData<Ctx>,
> > );
> >
> > +/// Represents the PCI configuration space of a device.
> > +///
> > +/// Provides typed read and write accessors for configuration
> > registers +/// using the standard `pci_read_config_*` and
> > `pci_write_config_*` helpers. +///
> > +/// The generic const parameter `SIZE` can be used to indicate the
> > +/// maximum size of the configuration space (e.g. 256 bytes for
> > legacy, +/// 4096 bytes for extended config space). The actual size
> > is obtained +/// from the underlying `struct pci_dev` via
> > [`Device::cfg_size`]. +pub struct ConfigSpace<'a, const SIZE: usize
> > = { ConfigSpaceSize::Extended as usize }> {
> > + pdev: &'a Device<device::Core>,
> > +}
> > +
> > +macro_rules! call_config_read {
> > + (infallible, $c_fn:ident, $self:ident, $ty:ty, $addr:expr) =>
> > {{
> > + let mut val: $ty = 0;
> > + let ret = unsafe { bindings::$c_fn($self.pdev.as_raw(),
> > $addr as i32, &mut val) };
> > + match ret {
> > + 0 => val,
> > + _ => !0,
> > + }
>
> I think the match is not needed, the value should already be set
> accordingly.
>
> > + }};
> > +/// Represents the size of a PCI configuration space.
> > +///
> > +/// PCI devices can have either a *normal* (legacy) configuration
> > space of 256 bytes, +/// or an *extended* configuration space of
> > 4096 bytes as defined in the PCI Express +/// specification.
> > +pub enum ConfigSpaceSize {
>
> I think this should be [repr(usize)].
>
> > + /// 256-byte legacy PCI configuration space.
> > + Normal = 256,
> > +
> > + /// 4096-byte PCIe extended configuration space.
> > + Extended = 4096,
> > +}
> > +
> > impl Device {
> > /// Returns the PCI vendor ID as [`Vendor`].
> > ///
> > @@ -514,6 +625,17 @@ pub fn pci_class(&self) -> Class {
> > // SAFETY: `self.as_raw` is a valid pointer to a `struct
> > pci_dev`. Class::from_raw(unsafe { (*self.as_raw()).class })
> > }
> > +
> > + /// Returns the size of configuration space.
> > + fn cfg_size(&self) -> Result<ConfigSpaceSize> {
> > + // SAFETY: `self.as_raw` is a valid pointer to a `struct
> > pci_dev`.
> > + let size = unsafe { (*self.as_raw()).cfg_size };
> > + match size {
> > + 256 => Ok(ConfigSpaceSize::Normal),
> > + 4096 => Ok(ConfigSpaceSize::Extended),
> > + _ => Err(EINVAL),
>
> I'd add a debug_assert!() in this case.
>
> > + }
> > + }
> > }
> >
> > impl Device<device::Bound> {
> > @@ -591,6 +713,20 @@ pub fn set_master(&self) {
> > // SAFETY: `self.as_raw` is guaranteed to be a pointer to
> > a valid `struct pci_dev`. unsafe {
> > bindings::pci_set_master(self.as_raw()) }; }
> > +
> > + /// Return an initialized config space object.
> > + pub fn config_space<'a>(
> > + &'a self,
> > + ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Normal as usize
> > }>> {
>
> Let's add as_raw() to ConfigSpaceSize and use that instead.
>
> > + Ok(ConfigSpace { pdev: self })
> > + }
> > +
> > + /// Return an initialized config space object.
> > + pub fn config_space_exteneded<'a>(
> > + &'a self,
> > + ) -> Result<ConfigSpace<'a, { ConfigSpaceSize::Extended as
> > usize }>> {
> > + Ok(ConfigSpace { pdev: self })
> > + }
> > }
> >
> > // SAFETY: `Device` is a transparent wrapper of a type that
> > doesn't depend on `Device`'s generic --
> > 2.51.0
>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines
2025-11-04 15:41 ` Danilo Krummrich
@ 2025-11-04 16:42 ` Zhi Wang
2025-11-04 16:46 ` Danilo Krummrich
0 siblings, 1 reply; 11+ messages in thread
From: Zhi Wang @ 2025-11-04 16:42 UTC (permalink / raw)
To: Danilo Krummrich
Cc: rust-for-linux, linux-pci, linux-kernel, aliceryhl, bhelgaas,
kwilczynski, ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh,
lossin, a.hindborg, tmgross, markus.probst, helgaas, cjia, smitra,
ankita, aniketa, kwankhede, targupta, acourbot, joelagnelf,
jhubbard, zhiwang
On Tue, 04 Nov 2025 16:41:56 +0100
"Danilo Krummrich" <dakr@kernel.org> wrote:
> On Tue Nov 4, 2025 at 3:27 PM CET, Zhi Wang wrote:
> > + fn config_space(pdev: &pci::Device<Core>) -> Result {
> > + let config = pdev.config_space()?;
> > +
> > + // TODO: use the register!() macro for defining PCI
> > configuration space registers once it
> > + // has been move out of nova-core.
> > + dev_info!(
> > + pdev.as_ref(),
> > + "pci-testdev config space read8 rev ID: {:x}\n",
> > + config.read8(0x8)
> > + );
> > +
> > + dev_info!(
> > + pdev.as_ref(),
> > + "pci-testdev config space read16 vendor ID: {:x}\n",
> > + config.read16(0)
> > + );
> > +
> > + dev_info!(
> > + pdev.as_ref(),
> > + "pci-testdev config space read32 BAR 0: {:x}\n",
> > + config.read32(0x10)
> > + );
> > +
> > + dev_info!(
> > + pdev.as_ref(),
> > + "pci-testdev config space try_read8 rev ID: {:x}\n",
> > + config.try_read8(0x8)?
> > + );
> > +
> > + dev_info!(
> > + pdev.as_ref(),
> > + "pci-testdev config space try_read16 vendor ID:
> > {:x}\n",
> > + config.try_read16(0)?
> > + );
> > +
> > + dev_info!(
> > + pdev.as_ref(),
> > + "pci-testdev config space try_read32 BAR 0: {:x}\n",
> > + config.try_read32(0x10)?
> > + );
>
> If we want to demonstrate the fallible accessors we should try
> accesses outside the bounds of the requested config space size.
> However, that doesn't really make sense, because in this case the
> driver could have been calling config_space_extended() instead.
>
> So, I think the fallible versions don't really serve a purpose and we
> should probably drop them.
We can add them back if there is a use case in rust driver later.
Should I arrange the traits like below?
Io trait - Main trait + 32-bit access
|
| -- Common address/bound checks
|
| (accessor traits)
| -- Io Fallible trait - (MMIO backend implements)
| -- Io Infallible trait - (MMIO/ConfigSpace backend implements this)
|
| -- Io64 trait - For backend supports 64 bit access
| (accessor traits)
| -- Io64 Faillable trait (MMIO backend implements this)
| -- Io64 Infallible trait (MMIO backend implements this)
I am also thinking if we should keep 64-bit access accessor in the
backend implementation instead in the Io trait (like {read, write}
_relaxed), because I think few backend (PCI Config Space/I2C/SPI) would
support 64-bit atomic access except MMIO backend.
Z.
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines
2025-11-04 16:42 ` Zhi Wang
@ 2025-11-04 16:46 ` Danilo Krummrich
0 siblings, 0 replies; 11+ messages in thread
From: Danilo Krummrich @ 2025-11-04 16:46 UTC (permalink / raw)
To: Zhi Wang
Cc: rust-for-linux, linux-pci, linux-kernel, aliceryhl, bhelgaas,
kwilczynski, ojeda, alex.gaynor, boqun.feng, gary, bjorn3_gh,
lossin, a.hindborg, tmgross, markus.probst, helgaas, cjia, smitra,
ankita, aniketa, kwankhede, targupta, acourbot, joelagnelf,
jhubbard, zhiwang
On 11/4/25 5:42 PM, Zhi Wang wrote:
> Should I arrange the traits like below?
>
> Io trait - Main trait + 32-bit access
> |
> | -- Common address/bound checks
> |
> | (accessor traits)
> | -- Io Fallible trait - (MMIO backend implements)
> | -- Io Infallible trait - (MMIO/ConfigSpace backend implements this)
> |
> | -- Io64 trait - For backend supports 64 bit access
> | (accessor traits)
> | -- Io64 Faillable trait (MMIO backend implements this)
> | -- Io64 Infallible trait (MMIO backend implements this)
>
> I am also thinking if we should keep 64-bit access accessor in the
> backend implementation instead in the Io trait (like {read, write}
> _relaxed), because I think few backend (PCI Config Space/I2C/SPI) would
> support 64-bit atomic access except MMIO backend.
SGTM, I think it's fine to keep 64-bit in the MMIO backend for now, we can
always split it out into a separate trait once needed.
^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2025-11-04 16:47 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-11-04 14:27 [PATCH RESEND v4 0/4] rust: pci: add config space read/write support Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 1/4] rust: io: factor common I/O helpers into Io trait Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 2/4] rust: io: factor out MMIO read/write macros Zhi Wang
2025-11-04 14:27 ` [PATCH RESEND v4 3/4] rust: pci: add config space read/write support Zhi Wang
2025-11-04 15:36 ` Danilo Krummrich
2025-11-04 16:19 ` Zhi Wang
2025-11-04 15:38 ` Danilo Krummrich
2025-11-04 14:27 ` [PATCH RESEND v4 4/4] sample: rust: pci: add tests for config space routines Zhi Wang
2025-11-04 15:41 ` Danilo Krummrich
2025-11-04 16:42 ` Zhi Wang
2025-11-04 16:46 ` Danilo Krummrich
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