Re: [PATCH v3 06/12] gpu: nova-core: add Turing boot registers

["Alexandre Courbot" <acourbot@nvidia.com>]

On Tue Dec 9, 2025 at 8:17 AM JST, Timur Tabi wrote:
> Define some more GPU registers used to boot GSP-RM on Turing and GA100.
>
> Signed-off-by: Timur Tabi <ttabi@nvidia.com>
> ---
>  drivers/gpu/nova-core/regs.rs | 63 +++++++++++++++++++++++++++++++++++
>  1 file changed, 63 insertions(+)
>
> diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
> index 88bec1d4830b..2143869d27ba 100644
> --- a/drivers/gpu/nova-core/regs.rs
> +++ b/drivers/gpu/nova-core/regs.rs
> @@ -258,6 +258,11 @@ pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
>      6:6     swgen0 as bool;
>  });
>  
> +// Interrupt mask clear register. Writing 1 to a bit clears the corresponding interrupt mask.
> +register!(NV_PFALCON_FALCON_IRQMCLR @ PFalconBase[0x00000014] {
> +    31:0    value as u32;
> +});
> +

This register doesn't appear to be used in this series.

>  register!(NV_PFALCON_FALCON_MAILBOX0 @ PFalconBase[0x00000040] {
>      31:0    value as u32;
>  });
> @@ -266,6 +271,14 @@ pub(crate) fn vga_workspace_addr(self) -> Option<u64> {
>      31:0    value as u32;
>  });
>  
> +// Interface enable register.
> +register!(NV_PFALCON_FALCON_ITFEN @ PFalconBase[0x00000048] {
> +    0:0     ctxen as bool, "Context interface enable";
> +    1:1     mthden as bool, "Method interface enable";
> +    2:2     postwr as bool;
> +    4:4     secwl_cpuctl_alias as bool;
> +});
> +

Neither is this one.

>  // Used to store version information about the firmware running
>  // on the Falcon processor.
>  register!(NV_PFALCON_FALCON_OS @ PFalconBase[0x00000080] {
> @@ -307,6 +320,13 @@ pub(crate) fn mem_scrubbing_done(self) -> bool {
>      7:7     secure_stat as bool;
>  });
>  
> +impl NV_PFALCON_FALCON_DMACTL {
> +    /// Returns `true` if memory scrubbing is completed.
> +    pub(crate) fn mem_scrubbing_done(self) -> bool {
> +        !self.dmem_scrubbing() && !self.imem_scrubbing()
> +    }
> +}
> +
>  register!(NV_PFALCON_FALCON_DMATRFBASE @ PFalconBase[0x00000110] {
>      31:0    base as u32;
>  });
> @@ -353,6 +373,42 @@ pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self {
>      1:1     startcpu as bool;
>  });
>  
> +// Config memory base address. Specifies the upper address bits that must be matched
> +// to access the config aperture. The base may not be zero as that would conflict with DMEM.
> +register!(NV_PFALCON2_FALCON_CMEMBASE @ PFalcon2Base[0x00000160] {
> +    31:18     value as u16;
> +});

Or this one.

For the one that remains, please introduce them in the patch that adds
PIO support - that way they are introduced alongside the code that makes
use of them. `regs.rs` is not touched in the PIO patch, so this also
won't complicate review.