* [PATCH v11 01/12] gpu: nova-core: create falcon firmware DMA objects lazily
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 02/12] gpu: nova-core: falcon: add constant for memory block alignment Alexandre Courbot
` (12 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
When DMA was the only loading option for falcon firmwares, we decided to
store them in DMA objects as soon as they were loaded from disk and
patch them in-place to avoid having to do an extra copy.
This decision complicates the PIO loading patch considerably, and
actually does not even stand on its own when put into perspective with
the fact that it requires 8 unsafe statements in the code that wouldn't
exist if we stored the firmware into a `KVVec` and copied it into a DMA
object at the last minute.
The cost of the copy is, as can be expected, imperceptible at runtime.
Thus, switch to a lazy DMA object creation model and simplify our code
a bit. This will also have the nice side-effect of being more fit for
PIO loading.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 57 +++++++++++------
drivers/gpu/nova-core/firmware.rs | 38 ++++++------
drivers/gpu/nova-core/firmware/booter.rs | 33 +++++-----
drivers/gpu/nova-core/firmware/fwsec.rs | 103 +++++++++++--------------------
drivers/gpu/nova-core/gsp/boot.rs | 2 +-
5 files changed, 106 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 37bfee1d0949..8d444cf9d55c 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -2,12 +2,13 @@
//! Falcon microprocessor base support
-use core::ops::Deref;
-
use hal::FalconHal;
use kernel::{
- device,
+ device::{
+ self,
+ Device, //
+ },
dma::{
DmaAddress,
DmaMask, //
@@ -15,9 +16,7 @@
io::poll::read_poll_timeout,
prelude::*,
sync::aref::ARef,
- time::{
- Delta, //
- },
+ time::Delta,
};
use crate::{
@@ -351,6 +350,9 @@ pub(crate) struct FalconBromParams {
/// Trait for providing load parameters of falcon firmwares.
pub(crate) trait FalconLoadParams {
+ /// Returns the firmware data as a slice of bytes.
+ fn as_slice(&self) -> &[u8];
+
/// Returns the load parameters for Secure `IMEM`.
fn imem_sec_load_params(&self) -> FalconLoadTarget;
@@ -370,9 +372,8 @@ pub(crate) trait FalconLoadParams {
/// Trait for a falcon firmware.
///
-/// A falcon firmware can be loaded on a given engine, and is presented in the form of a DMA
-/// object.
-pub(crate) trait FalconFirmware: FalconLoadParams + Deref<Target = DmaObject> {
+/// A falcon firmware can be loaded on a given engine.
+pub(crate) trait FalconFirmware: FalconLoadParams {
/// Engine on which this firmware is to be loaded.
type Target: FalconEngine;
}
@@ -415,10 +416,10 @@ pub(crate) fn reset(&self, bar: &Bar0) -> Result {
/// `target_mem`.
///
/// `sec` is set if the loaded firmware is expected to run in secure mode.
- fn dma_wr<F: FalconFirmware<Target = E>>(
+ fn dma_wr(
&self,
bar: &Bar0,
- fw: &F,
+ dma_obj: &DmaObject,
target_mem: FalconMem,
load_offsets: FalconLoadTarget,
) -> Result {
@@ -430,11 +431,11 @@ fn dma_wr<F: FalconFirmware<Target = E>>(
// For DMEM we can fold the start offset into the DMA handle.
let (src_start, dma_start) = match target_mem {
FalconMem::ImemSecure | FalconMem::ImemNonSecure => {
- (load_offsets.src_start, fw.dma_handle())
+ (load_offsets.src_start, dma_obj.dma_handle())
}
FalconMem::Dmem => (
0,
- fw.dma_handle_with_offset(load_offsets.src_start.into_safe_cast())?,
+ dma_obj.dma_handle_with_offset(load_offsets.src_start.into_safe_cast())?,
),
};
if dma_start % DmaAddress::from(DMA_LEN) > 0 {
@@ -466,7 +467,7 @@ fn dma_wr<F: FalconFirmware<Target = E>>(
dev_err!(self.dev, "DMA transfer length overflow\n");
return Err(EOVERFLOW);
}
- Some(upper_bound) if usize::from_safe_cast(upper_bound) > fw.size() => {
+ Some(upper_bound) if usize::from_safe_cast(upper_bound) > dma_obj.size() => {
dev_err!(self.dev, "DMA transfer goes beyond range of DMA object\n");
return Err(EINVAL);
}
@@ -515,7 +516,12 @@ fn dma_wr<F: FalconFirmware<Target = E>>(
}
/// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the falcon to run it.
- fn dma_load<F: FalconFirmware<Target = E>>(&self, bar: &Bar0, fw: &F) -> Result {
+ fn dma_load<F: FalconFirmware<Target = E>>(
+ &self,
+ dev: &Device<device::Bound>,
+ bar: &Bar0,
+ fw: &F,
+ ) -> Result {
// The Non-Secure section only exists on firmware used by Turing and GA100, and
// those platforms do not use DMA.
if fw.imem_ns_load_params().is_some() {
@@ -523,14 +529,22 @@ fn dma_load<F: FalconFirmware<Target = E>>(&self, bar: &Bar0, fw: &F) -> Result
return Err(EINVAL);
}
+ // Create DMA object with firmware content as the source of the DMA engine.
+ let dma_obj = DmaObject::from_data(dev, fw.as_slice())?;
+
self.dma_reset(bar);
regs::NV_PFALCON_FBIF_TRANSCFG::update(bar, &E::ID, 0, |v| {
v.set_target(FalconFbifTarget::CoherentSysmem)
.set_mem_type(FalconFbifMemType::Physical)
});
- self.dma_wr(bar, fw, FalconMem::ImemSecure, fw.imem_sec_load_params())?;
- self.dma_wr(bar, fw, FalconMem::Dmem, fw.dmem_load_params())?;
+ self.dma_wr(
+ bar,
+ &dma_obj,
+ FalconMem::ImemSecure,
+ fw.imem_sec_load_params(),
+ )?;
+ self.dma_wr(bar, &dma_obj, FalconMem::Dmem, fw.dmem_load_params())?;
self.hal.program_brom(self, bar, &fw.brom_params())?;
@@ -641,9 +655,14 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool {
}
// Load a firmware image into Falcon memory
- pub(crate) fn load<F: FalconFirmware<Target = E>>(&self, bar: &Bar0, fw: &F) -> Result {
+ pub(crate) fn load<F: FalconFirmware<Target = E>>(
+ &self,
+ dev: &Device<device::Bound>,
+ bar: &Bar0,
+ fw: &F,
+ ) -> Result {
match self.hal.load_method() {
- LoadMethod::Dma => self.dma_load(bar, fw),
+ LoadMethod::Dma => self.dma_load(dev, bar, fw),
LoadMethod::Pio => Err(ENOTSUPP),
}
}
diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
index 815e8000bf81..09b12ad546c2 100644
--- a/drivers/gpu/nova-core/firmware.rs
+++ b/drivers/gpu/nova-core/firmware.rs
@@ -15,7 +15,6 @@
};
use crate::{
- dma::DmaObject,
falcon::{
FalconFirmware,
FalconLoadTarget, //
@@ -292,7 +291,7 @@ impl SignedState for Unsigned {}
struct Signed;
impl SignedState for Signed {}
-/// A [`DmaObject`] containing a specific microcode ready to be loaded into a falcon.
+/// Microcode to be loaded into a specific falcon.
///
/// This is module-local and meant for sub-modules to use internally.
///
@@ -300,34 +299,33 @@ impl SignedState for Signed {}
/// before it can be loaded (with an exception for development hardware). The
/// [`Self::patch_signature`] and [`Self::no_patch_signature`] methods are used to transition the
/// firmware to its [`Signed`] state.
-struct FirmwareDmaObject<F: FalconFirmware, S: SignedState>(DmaObject, PhantomData<(F, S)>);
+struct FirmwareObject<F: FalconFirmware, S: SignedState>(KVVec<u8>, PhantomData<(F, S)>);
/// Trait for signatures to be patched directly into a given firmware.
///
/// This is module-local and meant for sub-modules to use internally.
trait FirmwareSignature<F: FalconFirmware>: AsRef<[u8]> {}
-impl<F: FalconFirmware> FirmwareDmaObject<F, Unsigned> {
- /// Patches the firmware at offset `sig_base_img` with `signature`.
+impl<F: FalconFirmware> FirmwareObject<F, Unsigned> {
+ /// Patches the firmware at offset `signature_start` with `signature`.
fn patch_signature<S: FirmwareSignature<F>>(
mut self,
signature: &S,
- sig_base_img: usize,
- ) -> Result<FirmwareDmaObject<F, Signed>> {
+ signature_start: usize,
+ ) -> Result<FirmwareObject<F, Signed>> {
let signature_bytes = signature.as_ref();
- if sig_base_img + signature_bytes.len() > self.0.size() {
- return Err(EINVAL);
- }
+ let signature_end = signature_start
+ .checked_add(signature_bytes.len())
+ .ok_or(EOVERFLOW)?;
+ let dst = self
+ .0
+ .get_mut(signature_start..signature_end)
+ .ok_or(EINVAL)?;
- // SAFETY: We are the only user of this object, so there cannot be any race.
- let dst = unsafe { self.0.start_ptr_mut().add(sig_base_img) };
+ // PANIC: `dst` and `signature_bytes` have the same length.
+ dst.copy_from_slice(signature_bytes);
- // SAFETY: `signature` and `dst` are valid, properly aligned, and do not overlap.
- unsafe {
- core::ptr::copy_nonoverlapping(signature_bytes.as_ptr(), dst, signature_bytes.len())
- };
-
- Ok(FirmwareDmaObject(self.0, PhantomData))
+ Ok(FirmwareObject(self.0, PhantomData))
}
/// Mark the firmware as signed without patching it.
@@ -335,8 +333,8 @@ fn patch_signature<S: FirmwareSignature<F>>(
/// This method is used to explicitly confirm that we do not need to sign the firmware, while
/// allowing us to continue as if it was. This is typically only needed for development
/// hardware.
- fn no_patch_signature(self) -> FirmwareDmaObject<F, Signed> {
- FirmwareDmaObject(self.0, PhantomData)
+ fn no_patch_signature(self) -> FirmwareObject<F, Signed> {
+ FirmwareObject(self.0, PhantomData)
}
}
diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-core/firmware/booter.rs
index ab374026b1f4..2b7166eaf283 100644
--- a/drivers/gpu/nova-core/firmware/booter.rs
+++ b/drivers/gpu/nova-core/firmware/booter.rs
@@ -4,10 +4,7 @@
//! running on [`Sec2`], that is used on Turing/Ampere to load the GSP firmware into the GSP falcon
//! (and optionally unload it through a separate firmware image).
-use core::{
- marker::PhantomData,
- ops::Deref, //
-};
+use core::marker::PhantomData;
use kernel::{
device,
@@ -16,7 +13,6 @@
};
use crate::{
- dma::DmaObject,
driver::Bar0,
falcon::{
sec2::Sec2,
@@ -28,7 +24,7 @@
},
firmware::{
BinFirmware,
- FirmwareDmaObject,
+ FirmwareObject,
FirmwareSignature,
Signed,
Unsigned, //
@@ -269,12 +265,15 @@ pub(crate) struct BooterFirmware {
// BROM falcon parameters.
brom_params: FalconBromParams,
// Device-mapped firmware image.
- ucode: FirmwareDmaObject<Self, Signed>,
+ ucode: FirmwareObject<Self, Signed>,
}
-impl FirmwareDmaObject<BooterFirmware, Unsigned> {
- fn new_booter(dev: &device::Device<device::Bound>, data: &[u8]) -> Result<Self> {
- DmaObject::from_data(dev, data).map(|ucode| Self(ucode, PhantomData))
+impl FirmwareObject<BooterFirmware, Unsigned> {
+ fn new_booter(data: &[u8]) -> Result<Self> {
+ let mut ucode = KVVec::new();
+ ucode.extend_from_slice(data, GFP_KERNEL)?;
+
+ Ok(Self(ucode, PhantomData))
}
}
@@ -328,7 +327,7 @@ pub(crate) fn new(
let ucode = bin_fw
.data()
.ok_or(EINVAL)
- .and_then(|data| FirmwareDmaObject::<Self, _>::new_booter(dev, data))?;
+ .and_then(FirmwareObject::<Self, _>::new_booter)?;
let ucode_signed = {
let mut signatures = hs_fw.signatures_iter()?.peekable();
@@ -400,6 +399,10 @@ pub(crate) fn new(
}
impl FalconLoadParams for BooterFirmware {
+ fn as_slice(&self) -> &[u8] {
+ self.ucode.0.as_slice()
+ }
+
fn imem_sec_load_params(&self) -> FalconLoadTarget {
self.imem_sec_load_target.clone()
}
@@ -425,14 +428,6 @@ fn boot_addr(&self) -> u32 {
}
}
-impl Deref for BooterFirmware {
- type Target = DmaObject;
-
- fn deref(&self) -> &Self::Target {
- &self.ucode.0
- }
-}
-
impl FalconFirmware for BooterFirmware {
type Target = Sec2;
}
diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-core/firmware/fwsec.rs
index df3d8de14ca1..7fff3acdaa73 100644
--- a/drivers/gpu/nova-core/firmware/fwsec.rs
+++ b/drivers/gpu/nova-core/firmware/fwsec.rs
@@ -10,10 +10,7 @@
//! - The command to be run, as this firmware can perform several tasks ;
//! - The ucode signature, so the GSP falcon can run FWSEC in HS mode.
-use core::{
- marker::PhantomData,
- ops::Deref, //
-};
+use core::marker::PhantomData;
use kernel::{
device::{
@@ -28,7 +25,6 @@
};
use crate::{
- dma::DmaObject,
driver::Bar0,
falcon::{
gsp::Gsp,
@@ -40,7 +36,7 @@
},
firmware::{
FalconUCodeDesc,
- FirmwareDmaObject,
+ FirmwareObject,
FirmwareSignature,
Signed,
Unsigned, //
@@ -174,52 +170,21 @@ fn as_ref(&self) -> &[u8] {
impl FirmwareSignature<FwsecFirmware> for Bcrt30Rsa3kSignature {}
-/// Reinterpret the area starting from `offset` in `fw` as an instance of `T` (which must implement
-/// [`FromBytes`]) and return a reference to it.
-///
-/// # Safety
-///
-/// * Callers must ensure that the device does not read/write to/from memory while the returned
-/// reference is live.
-/// * Callers must ensure that this call does not race with a write to the same region while
-/// the returned reference is live.
-unsafe fn transmute<T: Sized + FromBytes>(fw: &DmaObject, offset: usize) -> Result<&T> {
- // SAFETY: The safety requirements of the function guarantee the device won't read
- // or write to memory while the reference is alive and that this call won't race
- // with writes to the same memory region.
- T::from_bytes(unsafe { fw.as_slice(offset, size_of::<T>())? }).ok_or(EINVAL)
-}
-
-/// Reinterpret the area starting from `offset` in `fw` as a mutable instance of `T` (which must
-/// implement [`FromBytes`]) and return a reference to it.
-///
-/// # Safety
-///
-/// * Callers must ensure that the device does not read/write to/from memory while the returned
-/// slice is live.
-/// * Callers must ensure that this call does not race with a read or write to the same region
-/// while the returned slice is live.
-unsafe fn transmute_mut<T: Sized + FromBytes + AsBytes>(
- fw: &mut DmaObject,
- offset: usize,
-) -> Result<&mut T> {
- // SAFETY: The safety requirements of the function guarantee the device won't read
- // or write to memory while the reference is alive and that this call won't race
- // with writes or reads to the same memory region.
- T::from_bytes_mut(unsafe { fw.as_slice_mut(offset, size_of::<T>())? }).ok_or(EINVAL)
-}
-
/// The FWSEC microcode, extracted from the BIOS and to be run on the GSP falcon.
///
/// It is responsible for e.g. carving out the WPR2 region as the first step of the GSP bootflow.
pub(crate) struct FwsecFirmware {
/// Descriptor of the firmware.
desc: FalconUCodeDesc,
- /// GPU-accessible DMA object containing the firmware.
- ucode: FirmwareDmaObject<Self, Signed>,
+ /// Object containing the firmware binary.
+ ucode: FirmwareObject<Self, Signed>,
}
impl FalconLoadParams for FwsecFirmware {
+ fn as_slice(&self) -> &[u8] {
+ self.ucode.0.as_slice()
+ }
+
fn imem_sec_load_params(&self) -> FalconLoadTarget {
self.desc.imem_sec_load_params()
}
@@ -245,23 +210,15 @@ fn boot_addr(&self) -> u32 {
}
}
-impl Deref for FwsecFirmware {
- type Target = DmaObject;
-
- fn deref(&self) -> &Self::Target {
- &self.ucode.0
- }
-}
-
impl FalconFirmware for FwsecFirmware {
type Target = Gsp;
}
-impl FirmwareDmaObject<FwsecFirmware, Unsigned> {
- fn new_fwsec(dev: &Device<device::Bound>, bios: &Vbios, cmd: FwsecCommand) -> Result<Self> {
+impl FirmwareObject<FwsecFirmware, Unsigned> {
+ fn new_fwsec(bios: &Vbios, cmd: FwsecCommand) -> Result<Self> {
let desc = bios.fwsec_image().header()?;
- let ucode = bios.fwsec_image().ucode(&desc)?;
- let mut dma_object = DmaObject::from_data(dev, ucode)?;
+ let mut ucode = KVVec::new();
+ ucode.extend_from_slice(bios.fwsec_image().ucode(&desc)?, GFP_KERNEL)?;
let hdr_offset = desc
.imem_load_size()
@@ -269,8 +226,11 @@ fn new_fwsec(dev: &Device<device::Bound>, bios: &Vbios, cmd: FwsecCommand) -> Re
.map(usize::from_safe_cast)
.ok_or(EINVAL)?;
- // SAFETY: we have exclusive access to `dma_object`.
- let hdr: &FalconAppifHdrV1 = unsafe { transmute(&dma_object, hdr_offset) }?;
+ let hdr = ucode
+ .get(hdr_offset..)
+ .and_then(FalconAppifHdrV1::from_bytes_prefix)
+ .ok_or(EINVAL)?
+ .0;
if hdr.version != 1 {
return Err(EINVAL);
@@ -284,8 +244,11 @@ fn new_fwsec(dev: &Device<device::Bound>, bios: &Vbios, cmd: FwsecCommand) -> Re
.and_then(|o| o.checked_add(i.checked_mul(usize::from(hdr.entry_size))?))
.ok_or(EINVAL)?;
- // SAFETY: we have exclusive access to `dma_object`.
- let app: &FalconAppifV1 = unsafe { transmute(&dma_object, entry_offset) }?;
+ let app = ucode
+ .get(entry_offset..)
+ .and_then(FalconAppifV1::from_bytes_prefix)
+ .ok_or(EINVAL)?
+ .0;
if app.id != NVFW_FALCON_APPIF_ID_DMEMMAPPER {
continue;
@@ -298,9 +261,11 @@ fn new_fwsec(dev: &Device<device::Bound>, bios: &Vbios, cmd: FwsecCommand) -> Re
.map(usize::from_safe_cast)
.ok_or(EINVAL)?;
- let dmem_mapper: &mut FalconAppifDmemmapperV3 =
- // SAFETY: we have exclusive access to `dma_object`.
- unsafe { transmute_mut(&mut dma_object, dmem_mapper_offset) }?;
+ let dmem_mapper = ucode
+ .get_mut(dmem_mapper_offset..)
+ .and_then(FalconAppifDmemmapperV3::from_bytes_mut_prefix)
+ .ok_or(EINVAL)?
+ .0;
dmem_mapper.init_cmd = match cmd {
FwsecCommand::Frts { .. } => NVFW_FALCON_APPIF_DMEMMAPPER_CMD_FRTS,
@@ -314,9 +279,11 @@ fn new_fwsec(dev: &Device<device::Bound>, bios: &Vbios, cmd: FwsecCommand) -> Re
.map(usize::from_safe_cast)
.ok_or(EINVAL)?;
- let frts_cmd: &mut FrtsCmd =
- // SAFETY: we have exclusive access to `dma_object`.
- unsafe { transmute_mut(&mut dma_object, frts_cmd_offset) }?;
+ let frts_cmd = ucode
+ .get_mut(frts_cmd_offset..)
+ .and_then(FrtsCmd::from_bytes_mut_prefix)
+ .ok_or(EINVAL)?
+ .0;
frts_cmd.read_vbios = ReadVbios {
ver: 1,
@@ -340,7 +307,7 @@ fn new_fwsec(dev: &Device<device::Bound>, bios: &Vbios, cmd: FwsecCommand) -> Re
}
// Return early as we found and patched the DMEMMAPPER region.
- return Ok(Self(dma_object, PhantomData));
+ return Ok(Self(ucode, PhantomData));
}
Err(ENOTSUPP)
@@ -357,7 +324,7 @@ pub(crate) fn new(
bios: &Vbios,
cmd: FwsecCommand,
) -> Result<Self> {
- let ucode_dma = FirmwareDmaObject::<Self, _>::new_fwsec(dev, bios, cmd)?;
+ let ucode_dma = FirmwareObject::<Self, _>::new_fwsec(bios, cmd)?;
// Patch signature if needed.
let desc = bios.fwsec_image().header()?;
@@ -429,7 +396,7 @@ pub(crate) fn run(
.reset(bar)
.inspect_err(|e| dev_err!(dev, "Failed to reset GSP falcon: {:?}\n", e))?;
falcon
- .load(bar, self)
+ .load(dev, bar, self)
.inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware: {:?}\n", e))?;
let (mbox0, _) = falcon
.boot(bar, Some(0), None)
diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/boot.rs
index c56029f444cb..78957ed8814f 100644
--- a/drivers/gpu/nova-core/gsp/boot.rs
+++ b/drivers/gpu/nova-core/gsp/boot.rs
@@ -178,7 +178,7 @@ pub(crate) fn boot(
);
sec2_falcon.reset(bar)?;
- sec2_falcon.load(bar, &booter_loader)?;
+ sec2_falcon.load(dev, bar, &booter_loader)?;
let wpr_handle = wpr_meta.dma_handle();
let (mbox0, mbox1) = sec2_falcon.boot(
bar,
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v11 02/12] gpu: nova-core: falcon: add constant for memory block alignment
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 01/12] gpu: nova-core: create falcon firmware DMA objects lazily Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 03/12] gpu: nova-core: falcon: rename load parameters to reflect DMA dependency Alexandre Courbot
` (11 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
Falcon memory blocks are 256 bytes in size. This is a hard constant on
all models.
This value was hardcoded, so turn it into a documented constant. It will
also become useful with the PIO loading code.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 6 +++++-
1 file changed, 5 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 8d444cf9d55c..31217cd3a795 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -25,6 +25,7 @@
falcon::hal::LoadMethod,
gpu::Chipset,
num::{
+ self,
FromSafeCast,
IntoSafeCast, //
},
@@ -36,6 +37,9 @@
mod hal;
pub(crate) mod sec2;
+/// Alignment (in bytes) of falcon memory blocks.
+pub(crate) const MEM_BLOCK_ALIGNMENT: usize = 256;
+
// TODO[FPRI]: Replace with `ToPrimitive`.
macro_rules! impl_from_enum_to_u8 {
($enum_type:ty) => {
@@ -423,7 +427,7 @@ fn dma_wr(
target_mem: FalconMem,
load_offsets: FalconLoadTarget,
) -> Result {
- const DMA_LEN: u32 = 256;
+ const DMA_LEN: u32 = num::usize_into_u32::<{ MEM_BLOCK_ALIGNMENT }>();
// For IMEM, we want to use the start offset as a virtual address tag for each page, since
// code addresses in the firmware (and the boot vector) are virtual.
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v11 03/12] gpu: nova-core: falcon: rename load parameters to reflect DMA dependency
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 01/12] gpu: nova-core: create falcon firmware DMA objects lazily Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 02/12] gpu: nova-core: falcon: add constant for memory block alignment Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 6:23 ` Eliot Courtney
2026-03-06 4:52 ` [PATCH v11 04/12] gpu: nova-core: falcon: remove FalconFirmware's dependency on FalconDmaLoadable Alexandre Courbot
` (10 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
The current `FalconLoadParams` and `FalconLoadTarget` types are fit for
DMA loading, but not so much for PIO loading which will require its own
types. Start by renaming them to something that indicates that they are
indeed DMA-related.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 19 ++++++++++---------
drivers/gpu/nova-core/firmware.rs | 30 +++++++++++++++---------------
drivers/gpu/nova-core/firmware/booter.rs | 24 ++++++++++++------------
drivers/gpu/nova-core/firmware/fwsec.rs | 12 ++++++------
4 files changed, 43 insertions(+), 42 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 31217cd3a795..9eb827477e5e 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -330,9 +330,10 @@ pub(crate) trait FalconEngine:
const ID: Self;
}
-/// Represents a portion of the firmware to be loaded into a particular memory (e.g. IMEM or DMEM).
+/// Represents a portion of the firmware to be loaded into a particular memory (e.g. IMEM or DMEM)
+/// using DMA.
#[derive(Debug, Clone)]
-pub(crate) struct FalconLoadTarget {
+pub(crate) struct FalconDmaLoadTarget {
/// Offset from the start of the source object to copy from.
pub(crate) src_start: u32,
/// Offset from the start of the destination memory to copy into.
@@ -352,20 +353,20 @@ pub(crate) struct FalconBromParams {
pub(crate) ucode_id: u8,
}
-/// Trait for providing load parameters of falcon firmwares.
-pub(crate) trait FalconLoadParams {
+/// Trait implemented by falcon firmwares that can be loaded using DMA.
+pub(crate) trait FalconDmaLoadable {
/// Returns the firmware data as a slice of bytes.
fn as_slice(&self) -> &[u8];
/// Returns the load parameters for Secure `IMEM`.
- fn imem_sec_load_params(&self) -> FalconLoadTarget;
+ fn imem_sec_load_params(&self) -> FalconDmaLoadTarget;
/// Returns the load parameters for Non-Secure `IMEM`,
/// used only on Turing and GA100.
- fn imem_ns_load_params(&self) -> Option<FalconLoadTarget>;
+ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget>;
/// Returns the load parameters for `DMEM`.
- fn dmem_load_params(&self) -> FalconLoadTarget;
+ fn dmem_load_params(&self) -> FalconDmaLoadTarget;
/// Returns the parameters to write into the BROM registers.
fn brom_params(&self) -> FalconBromParams;
@@ -377,7 +378,7 @@ pub(crate) trait FalconLoadParams {
/// Trait for a falcon firmware.
///
/// A falcon firmware can be loaded on a given engine.
-pub(crate) trait FalconFirmware: FalconLoadParams {
+pub(crate) trait FalconFirmware: FalconDmaLoadable {
/// Engine on which this firmware is to be loaded.
type Target: FalconEngine;
}
@@ -425,7 +426,7 @@ fn dma_wr(
bar: &Bar0,
dma_obj: &DmaObject,
target_mem: FalconMem,
- load_offsets: FalconLoadTarget,
+ load_offsets: FalconDmaLoadTarget,
) -> Result {
const DMA_LEN: u32 = num::usize_into_u32::<{ MEM_BLOCK_ALIGNMENT }>();
diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
index 09b12ad546c2..677e1dac6d9f 100644
--- a/drivers/gpu/nova-core/firmware.rs
+++ b/drivers/gpu/nova-core/firmware.rs
@@ -16,8 +16,8 @@
use crate::{
falcon::{
+ FalconDmaLoadTarget, //
FalconFirmware,
- FalconLoadTarget, //
},
gpu,
num::{
@@ -170,9 +170,9 @@ fn size(&self) -> usize {
((hdr & HDR_SIZE_MASK) >> HDR_SIZE_SHIFT).into_safe_cast()
}
- fn imem_sec_load_params(&self) -> FalconLoadTarget;
- fn imem_ns_load_params(&self) -> Option<FalconLoadTarget>;
- fn dmem_load_params(&self) -> FalconLoadTarget;
+ fn imem_sec_load_params(&self) -> FalconDmaLoadTarget;
+ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget>;
+ fn dmem_load_params(&self) -> FalconDmaLoadTarget;
}
impl FalconUCodeDescriptor for FalconUCodeDescV2 {
@@ -204,24 +204,24 @@ fn signature_versions(&self) -> u16 {
0
}
- fn imem_sec_load_params(&self) -> FalconLoadTarget {
- FalconLoadTarget {
+ fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
+ FalconDmaLoadTarget {
src_start: 0,
dst_start: self.imem_sec_base,
len: self.imem_sec_size,
}
}
- fn imem_ns_load_params(&self) -> Option<FalconLoadTarget> {
- Some(FalconLoadTarget {
+ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
+ Some(FalconDmaLoadTarget {
src_start: 0,
dst_start: self.imem_phys_base,
len: self.imem_load_size.checked_sub(self.imem_sec_size)?,
})
}
- fn dmem_load_params(&self) -> FalconLoadTarget {
- FalconLoadTarget {
+ fn dmem_load_params(&self) -> FalconDmaLoadTarget {
+ FalconDmaLoadTarget {
src_start: self.dmem_offset,
dst_start: self.dmem_phys_base,
len: self.dmem_load_size,
@@ -258,21 +258,21 @@ fn signature_versions(&self) -> u16 {
self.signature_versions
}
- fn imem_sec_load_params(&self) -> FalconLoadTarget {
- FalconLoadTarget {
+ fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
+ FalconDmaLoadTarget {
src_start: 0,
dst_start: self.imem_phys_base,
len: self.imem_load_size,
}
}
- fn imem_ns_load_params(&self) -> Option<FalconLoadTarget> {
+ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
// Not used on V3 platforms
None
}
- fn dmem_load_params(&self) -> FalconLoadTarget {
- FalconLoadTarget {
+ fn dmem_load_params(&self) -> FalconDmaLoadTarget {
+ FalconDmaLoadTarget {
src_start: self.imem_load_size,
dst_start: self.dmem_phys_base,
len: self.dmem_load_size,
diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-core/firmware/booter.rs
index 2b7166eaf283..c5963f79a08e 100644
--- a/drivers/gpu/nova-core/firmware/booter.rs
+++ b/drivers/gpu/nova-core/firmware/booter.rs
@@ -18,9 +18,9 @@
sec2::Sec2,
Falcon,
FalconBromParams,
+ FalconDmaLoadTarget, //
+ FalconDmaLoadable,
FalconFirmware,
- FalconLoadParams,
- FalconLoadTarget, //
},
firmware::{
BinFirmware,
@@ -256,12 +256,12 @@ impl<'a> FirmwareSignature<BooterFirmware> for BooterSignature<'a> {}
/// The `Booter` loader firmware, responsible for loading the GSP.
pub(crate) struct BooterFirmware {
// Load parameters for Secure `IMEM` falcon memory.
- imem_sec_load_target: FalconLoadTarget,
+ imem_sec_load_target: FalconDmaLoadTarget,
// Load parameters for Non-Secure `IMEM` falcon memory,
// used only on Turing and GA100
- imem_ns_load_target: Option<FalconLoadTarget>,
+ imem_ns_load_target: Option<FalconDmaLoadTarget>,
// Load parameters for `DMEM` falcon memory.
- dmem_load_target: FalconLoadTarget,
+ dmem_load_target: FalconDmaLoadTarget,
// BROM falcon parameters.
brom_params: FalconBromParams,
// Device-mapped firmware image.
@@ -370,7 +370,7 @@ pub(crate) fn new(
let (imem_sec_dst_start, imem_ns_load_target) = if chipset <= Chipset::GA100 {
(
app0.offset,
- Some(FalconLoadTarget {
+ Some(FalconDmaLoadTarget {
src_start: 0,
dst_start: load_hdr.os_code_offset,
len: load_hdr.os_code_size,
@@ -381,13 +381,13 @@ pub(crate) fn new(
};
Ok(Self {
- imem_sec_load_target: FalconLoadTarget {
+ imem_sec_load_target: FalconDmaLoadTarget {
src_start: app0.offset,
dst_start: imem_sec_dst_start,
len: app0.len,
},
imem_ns_load_target,
- dmem_load_target: FalconLoadTarget {
+ dmem_load_target: FalconDmaLoadTarget {
src_start: load_hdr.os_data_offset,
dst_start: 0,
len: load_hdr.os_data_size,
@@ -398,20 +398,20 @@ pub(crate) fn new(
}
}
-impl FalconLoadParams for BooterFirmware {
+impl FalconDmaLoadable for BooterFirmware {
fn as_slice(&self) -> &[u8] {
self.ucode.0.as_slice()
}
- fn imem_sec_load_params(&self) -> FalconLoadTarget {
+ fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
self.imem_sec_load_target.clone()
}
- fn imem_ns_load_params(&self) -> Option<FalconLoadTarget> {
+ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
self.imem_ns_load_target.clone()
}
- fn dmem_load_params(&self) -> FalconLoadTarget {
+ fn dmem_load_params(&self) -> FalconDmaLoadTarget {
self.dmem_load_target.clone()
}
diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-core/firmware/fwsec.rs
index 7fff3acdaa73..d5bb7d279fa7 100644
--- a/drivers/gpu/nova-core/firmware/fwsec.rs
+++ b/drivers/gpu/nova-core/firmware/fwsec.rs
@@ -30,9 +30,9 @@
gsp::Gsp,
Falcon,
FalconBromParams,
+ FalconDmaLoadTarget, //
+ FalconDmaLoadable,
FalconFirmware,
- FalconLoadParams,
- FalconLoadTarget, //
},
firmware::{
FalconUCodeDesc,
@@ -180,20 +180,20 @@ pub(crate) struct FwsecFirmware {
ucode: FirmwareObject<Self, Signed>,
}
-impl FalconLoadParams for FwsecFirmware {
+impl FalconDmaLoadable for FwsecFirmware {
fn as_slice(&self) -> &[u8] {
self.ucode.0.as_slice()
}
- fn imem_sec_load_params(&self) -> FalconLoadTarget {
+ fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
self.desc.imem_sec_load_params()
}
- fn imem_ns_load_params(&self) -> Option<FalconLoadTarget> {
+ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
self.desc.imem_ns_load_params()
}
- fn dmem_load_params(&self) -> FalconLoadTarget {
+ fn dmem_load_params(&self) -> FalconDmaLoadTarget {
self.desc.dmem_load_params()
}
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v11 03/12] gpu: nova-core: falcon: rename load parameters to reflect DMA dependency
2026-03-06 4:52 ` [PATCH v11 03/12] gpu: nova-core: falcon: rename load parameters to reflect DMA dependency Alexandre Courbot
@ 2026-03-06 6:23 ` Eliot Courtney
0 siblings, 0 replies; 31+ messages in thread
From: Eliot Courtney @ 2026-03-06 6:23 UTC (permalink / raw)
To: Alexandre Courbot, Danilo Krummrich, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel, dri-devel
On Fri Mar 6, 2026 at 1:52 PM JST, Alexandre Courbot wrote:
> The current `FalconLoadParams` and `FalconLoadTarget` types are fit for
> DMA loading, but not so much for PIO loading which will require its own
> types. Start by renaming them to something that indicates that they are
> indeed DMA-related.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
> --- a/drivers/gpu/nova-core/firmware.rs
> +++ b/drivers/gpu/nova-core/firmware.rs
> @@ -16,8 +16,8 @@
>
> use crate::{
> falcon::{
> + FalconDmaLoadTarget, //
> FalconFirmware,
> - FalconLoadTarget, //
nit: // guard on wrong line I think?, here and other places in this diff
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v11 04/12] gpu: nova-core: falcon: remove FalconFirmware's dependency on FalconDmaLoadable
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (2 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 03/12] gpu: nova-core: falcon: rename load parameters to reflect DMA dependency Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 05/12] gpu: nova-core: move brom_params and boot_addr to FalconFirmware Alexandre Courbot
` (9 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
Not all firmware is necessarily loaded by DMA. Remove the requirement
for `FalconFirmware` to implement `FalconDmaLoadable`, and adapt
`Falcon`'s methods constraints accordingly.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 9eb827477e5e..450431804e1c 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -378,7 +378,7 @@ pub(crate) trait FalconDmaLoadable {
/// Trait for a falcon firmware.
///
/// A falcon firmware can be loaded on a given engine.
-pub(crate) trait FalconFirmware: FalconDmaLoadable {
+pub(crate) trait FalconFirmware {
/// Engine on which this firmware is to be loaded.
type Target: FalconEngine;
}
@@ -521,7 +521,7 @@ fn dma_wr(
}
/// Perform a DMA load into `IMEM` and `DMEM` of `fw`, and prepare the falcon to run it.
- fn dma_load<F: FalconFirmware<Target = E>>(
+ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>(
&self,
dev: &Device<device::Bound>,
bar: &Bar0,
@@ -660,7 +660,7 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool {
}
// Load a firmware image into Falcon memory
- pub(crate) fn load<F: FalconFirmware<Target = E>>(
+ pub(crate) fn load<F: FalconFirmware<Target = E> + FalconDmaLoadable>(
&self,
dev: &Device<device::Bound>,
bar: &Bar0,
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v11 05/12] gpu: nova-core: move brom_params and boot_addr to FalconFirmware
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (3 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 04/12] gpu: nova-core: falcon: remove FalconFirmware's dependency on FalconDmaLoadable Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 06/12] gpu: nova-core: add PIO support for loading firmware images Alexandre Courbot
` (8 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
These methods are relevant no matter the loading method used, thus move
them to the common `FalconFirmware` trait.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 12 ++++++------
drivers/gpu/nova-core/firmware/booter.rs | 8 ++++----
drivers/gpu/nova-core/firmware/fwsec.rs | 8 ++++----
3 files changed, 14 insertions(+), 14 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 450431804e1c..c90664efb0c5 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -367,12 +367,6 @@ pub(crate) trait FalconDmaLoadable {
/// Returns the load parameters for `DMEM`.
fn dmem_load_params(&self) -> FalconDmaLoadTarget;
-
- /// Returns the parameters to write into the BROM registers.
- fn brom_params(&self) -> FalconBromParams;
-
- /// Returns the start address of the firmware.
- fn boot_addr(&self) -> u32;
}
/// Trait for a falcon firmware.
@@ -381,6 +375,12 @@ pub(crate) trait FalconDmaLoadable {
pub(crate) trait FalconFirmware {
/// Engine on which this firmware is to be loaded.
type Target: FalconEngine;
+
+ /// Returns the parameters to write into the BROM registers.
+ fn brom_params(&self) -> FalconBromParams;
+
+ /// Returns the start address of the firmware.
+ fn boot_addr(&self) -> u32;
}
/// Contains the base parameters common to all Falcon instances.
diff --git a/drivers/gpu/nova-core/firmware/booter.rs b/drivers/gpu/nova-core/firmware/booter.rs
index c5963f79a08e..2dccbdd1b558 100644
--- a/drivers/gpu/nova-core/firmware/booter.rs
+++ b/drivers/gpu/nova-core/firmware/booter.rs
@@ -414,6 +414,10 @@ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
fn dmem_load_params(&self) -> FalconDmaLoadTarget {
self.dmem_load_target.clone()
}
+}
+
+impl FalconFirmware for BooterFirmware {
+ type Target = Sec2;
fn brom_params(&self) -> FalconBromParams {
self.brom_params.clone()
@@ -427,7 +431,3 @@ fn boot_addr(&self) -> u32 {
}
}
}
-
-impl FalconFirmware for BooterFirmware {
- type Target = Sec2;
-}
diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-core/firmware/fwsec.rs
index d5bb7d279fa7..87495d1d6cac 100644
--- a/drivers/gpu/nova-core/firmware/fwsec.rs
+++ b/drivers/gpu/nova-core/firmware/fwsec.rs
@@ -196,6 +196,10 @@ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
fn dmem_load_params(&self) -> FalconDmaLoadTarget {
self.desc.dmem_load_params()
}
+}
+
+impl FalconFirmware for FwsecFirmware {
+ type Target = Gsp;
fn brom_params(&self) -> FalconBromParams {
FalconBromParams {
@@ -210,10 +214,6 @@ fn boot_addr(&self) -> u32 {
}
}
-impl FalconFirmware for FwsecFirmware {
- type Target = Gsp;
-}
-
impl FirmwareObject<FwsecFirmware, Unsigned> {
fn new_fwsec(bios: &Vbios, cmd: FwsecCommand) -> Result<Self> {
let desc = bios.fwsec_image().header()?;
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v11 06/12] gpu: nova-core: add PIO support for loading firmware images
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (4 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 05/12] gpu: nova-core: move brom_params and boot_addr to FalconFirmware Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 07/12] gpu: nova-core: falcon: remove unwarranted safety check in dma_load Alexandre Courbot
` (7 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
From: Timur Tabi <ttabi@nvidia.com>
Turing and GA100 use programmed I/O (PIO) instead of DMA to upload
firmware images into Falcon memory.
Signed-off-by: Timur Tabi <ttabi@nvidia.com>
Co-developed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 218 +++++++++++++++++++++++++++++++++++-
drivers/gpu/nova-core/falcon/hal.rs | 6 +-
drivers/gpu/nova-core/regs.rs | 30 +++++
3 files changed, 251 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index c90664efb0c5..2168ef2c5148 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -367,6 +367,127 @@ pub(crate) trait FalconDmaLoadable {
/// Returns the load parameters for `DMEM`.
fn dmem_load_params(&self) -> FalconDmaLoadTarget;
+
+ /// Returns an adapter that provides the required parameter to load this firmware using PIO.
+ ///
+ /// This can only fail if some `u32` fields cannot be converted to `u16`, or if the indices in
+ /// the headers are invalid.
+ fn try_as_pio_loadable(&self) -> Result<FalconDmaFirmwarePioAdapter<'_, Self>> {
+ let new_pio_imem = |params: FalconDmaLoadTarget, secure| {
+ let start = usize::from_safe_cast(params.src_start);
+ let end = start + usize::from_safe_cast(params.len);
+ let data = self.as_slice().get(start..end).ok_or(EINVAL)?;
+
+ let dst_start = u16::try_from(params.dst_start).map_err(|_| EINVAL)?;
+
+ Ok::<_, Error>(FalconPioImemLoadTarget {
+ data,
+ dst_start,
+ secure,
+ start_tag: dst_start >> 8,
+ })
+ };
+
+ let imem_sec = new_pio_imem(self.imem_sec_load_params(), true)?;
+
+ let imem_ns = if let Some(params) = self.imem_ns_load_params() {
+ Some(new_pio_imem(params, false)?)
+ } else {
+ None
+ };
+
+ let dmem = {
+ let params = self.dmem_load_params();
+ let start = usize::from_safe_cast(params.src_start);
+ let end = start + usize::from_safe_cast(params.len);
+ let data = self.as_slice().get(start..end).ok_or(EINVAL)?;
+
+ let dst_start = u16::try_from(params.dst_start).map_err(|_| EINVAL)?;
+
+ FalconPioDmemLoadTarget { data, dst_start }
+ };
+
+ Ok(FalconDmaFirmwarePioAdapter {
+ fw: self,
+ imem_sec,
+ imem_ns,
+ dmem,
+ })
+ }
+}
+
+/// Represents a portion of the firmware to be loaded into IMEM using PIO.
+#[derive(Clone)]
+pub(crate) struct FalconPioImemLoadTarget<'a> {
+ pub(crate) data: &'a [u8],
+ pub(crate) dst_start: u16,
+ pub(crate) secure: bool,
+ pub(crate) start_tag: u16,
+}
+
+/// Represents a portion of the firmware to be loaded into DMEM using PIO.
+#[derive(Clone)]
+pub(crate) struct FalconPioDmemLoadTarget<'a> {
+ pub(crate) data: &'a [u8],
+ pub(crate) dst_start: u16,
+}
+
+/// Trait for providing PIO load parameters of falcon firmwares.
+pub(crate) trait FalconPioLoadable {
+ /// Returns the load parameters for Secure `IMEM`, if any.
+ fn imem_sec_load_params(&self) -> Option<FalconPioImemLoadTarget<'_>>;
+
+ /// Returns the load parameters for Non-Secure `IMEM`, if any.
+ fn imem_ns_load_params(&self) -> Option<FalconPioImemLoadTarget<'_>>;
+
+ /// Returns the load parameters for `DMEM`.
+ fn dmem_load_params(&self) -> FalconPioDmemLoadTarget<'_>;
+}
+
+/// Adapter type that makes any DMA-loadable firmware also loadable via PIO.
+///
+/// Created using [`FalconDmaLoadable::try_as_pio_loadable`].
+pub(crate) struct FalconDmaFirmwarePioAdapter<'a, T: FalconDmaLoadable + ?Sized> {
+ /// Reference to the DMA firmware.
+ fw: &'a T,
+ /// Validated secure IMEM parameters.
+ imem_sec: FalconPioImemLoadTarget<'a>,
+ /// Validated non-secure IMEM parameters.
+ imem_ns: Option<FalconPioImemLoadTarget<'a>>,
+ /// Validated DMEM parameters.
+ dmem: FalconPioDmemLoadTarget<'a>,
+}
+
+impl<'a, T> FalconPioLoadable for FalconDmaFirmwarePioAdapter<'a, T>
+where
+ T: FalconDmaLoadable + ?Sized,
+{
+ fn imem_sec_load_params(&self) -> Option<FalconPioImemLoadTarget<'_>> {
+ Some(self.imem_sec.clone())
+ }
+
+ fn imem_ns_load_params(&self) -> Option<FalconPioImemLoadTarget<'_>> {
+ self.imem_ns.clone()
+ }
+
+ fn dmem_load_params(&self) -> FalconPioDmemLoadTarget<'_> {
+ self.dmem.clone()
+ }
+}
+
+impl<'a, T> FalconFirmware for FalconDmaFirmwarePioAdapter<'a, T>
+where
+ T: FalconDmaLoadable + FalconFirmware + ?Sized,
+{
+ type Target = <T as FalconFirmware>::Target;
+
+ fn brom_params(&self) -> FalconBromParams {
+ self.fw.brom_params()
+ }
+
+ fn boot_addr(&self) -> u32 {
+ self.fw.boot_addr()
+ }
}
/// Trait for a falcon firmware.
@@ -417,6 +538,98 @@ pub(crate) fn reset(&self, bar: &Bar0) -> Result {
Ok(())
}
+ /// Falcons supports up to four ports, but we only ever use one, so just hard-code it.
+ const PIO_PORT: usize = 0;
+
+ /// Write a slice to Falcon IMEM memory using programmed I/O (PIO).
+ ///
+ /// Returns `EINVAL` if `img.len()` is not a multiple of 4.
+ fn pio_wr_imem_slice(&self, bar: &Bar0, load_offsets: FalconPioImemLoadTarget<'_>) -> Result {
+ // Rejecting misaligned images here allows us to avoid checking
+ // inside the loops.
+ if load_offsets.data.len() % 4 != 0 {
+ return Err(EINVAL);
+ }
+
+ regs::NV_PFALCON_FALCON_IMEMC::default()
+ .set_secure(load_offsets.secure)
+ .set_aincw(true)
+ .set_offs(load_offsets.dst_start)
+ .write(bar, &E::ID, Self::PIO_PORT);
+
+ for (n, block) in load_offsets.data.chunks(MEM_BLOCK_ALIGNMENT).enumerate() {
+ let n = u16::try_from(n)?;
+ let tag: u16 = load_offsets.start_tag.checked_add(n).ok_or(ERANGE)?;
+ regs::NV_PFALCON_FALCON_IMEMT::default().set_tag(tag).write(
+ bar,
+ &E::ID,
+ Self::PIO_PORT,
+ );
+ for word in block.chunks_exact(4) {
+ let w = [word[0], word[1], word[2], word[3]];
+ regs::NV_PFALCON_FALCON_IMEMD::default()
+ .set_data(u32::from_le_bytes(w))
+ .write(bar, &E::ID, Self::PIO_PORT);
+ }
+ }
+
+ Ok(())
+ }
+
+ /// Write a slice to Falcon DMEM memory using programmed I/O (PIO).
+ ///
+ /// Returns `EINVAL` if `img.len()` is not a multiple of 4.
+ fn pio_wr_dmem_slice(&self, bar: &Bar0, load_offsets: FalconPioDmemLoadTarget<'_>) -> Result {
+ // Rejecting misaligned images here allows us to avoid checking
+ // inside the loops.
+ if load_offsets.data.len() % 4 != 0 {
+ return Err(EINVAL);
+ }
+
+ regs::NV_PFALCON_FALCON_DMEMC::default()
+ .set_aincw(true)
+ .set_offs(load_offsets.dst_start)
+ .write(bar, &E::ID, Self::PIO_PORT);
+
+ for word in load_offsets.data.chunks_exact(4) {
+ let w = [word[0], word[1], word[2], word[3]];
+ regs::NV_PFALCON_FALCON_DMEMD::default()
+ .set_data(u32::from_le_bytes(w))
+ .write(bar, &E::ID, Self::PIO_PORT);
+ }
+
+ Ok(())
+ }
+
+ /// Perform a PIO copy into `IMEM` and `DMEM` of `fw`, and prepare the falcon to run it.
+ pub(crate) fn pio_load<F: FalconFirmware<Target = E> + FalconPioLoadable>(
+ &self,
+ bar: &Bar0,
+ fw: &F,
+ ) -> Result {
+ regs::NV_PFALCON_FBIF_CTL::read(bar, &E::ID)
+ .set_allow_phys_no_ctx(true)
+ .write(bar, &E::ID);
+
+ regs::NV_PFALCON_FALCON_DMACTL::default().write(bar, &E::ID);
+
+ if let Some(imem_ns) = fw.imem_ns_load_params() {
+ self.pio_wr_imem_slice(bar, imem_ns)?;
+ }
+ if let Some(imem_sec) = fw.imem_sec_load_params() {
+ self.pio_wr_imem_slice(bar, imem_sec)?;
+ }
+ self.pio_wr_dmem_slice(bar, fw.dmem_load_params())?;
+
+ self.hal.program_brom(self, bar, &fw.brom_params())?;
+
+ regs::NV_PFALCON_FALCON_BOOTVEC::default()
+ .set_value(fw.boot_addr())
+ .write(bar, &E::ID);
+
+ Ok(())
+ }
+
/// Perform a DMA write according to `load_offsets` from `dma_handle` into the falcon's
/// `target_mem`.
///
@@ -659,7 +872,8 @@ pub(crate) fn is_riscv_active(&self, bar: &Bar0) -> bool {
self.hal.is_riscv_active(bar)
}
- // Load a firmware image into Falcon memory
+ /// Load a firmware image into Falcon memory, using the preferred method for the current
+ /// chipset.
pub(crate) fn load<F: FalconFirmware<Target = E> + FalconDmaLoadable>(
&self,
dev: &Device<device::Bound>,
@@ -668,7 +882,7 @@ pub(crate) fn load<F: FalconFirmware<Target = E> + FalconDmaLoadable>(
) -> Result {
match self.hal.load_method() {
LoadMethod::Dma => self.dma_load(dev, bar, fw),
- LoadMethod::Pio => Err(ENOTSUPP),
+ LoadMethod::Pio => self.pio_load(bar, &fw.try_as_pio_loadable()?),
}
}
diff --git a/drivers/gpu/nova-core/falcon/hal.rs b/drivers/gpu/nova-core/falcon/hal.rs
index 89babd5f9325..a7e5ea8d0272 100644
--- a/drivers/gpu/nova-core/falcon/hal.rs
+++ b/drivers/gpu/nova-core/falcon/hal.rs
@@ -58,7 +58,11 @@ fn signature_reg_fuse_version(
/// Reset the falcon engine.
fn reset_eng(&self, bar: &Bar0) -> Result;
- /// returns the method needed to load data into Falcon memory
+ /// Returns the method used to load data into the falcon's memory.
+ ///
+ /// The only chipsets supporting PIO are those < GA102, and PIO is the preferred method for
+ /// these. For anything above, the PIO registers appear to be masked to the CPU, so DMA is the
+ /// only usable method.
fn load_method(&self) -> LoadMethod;
}
diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.rs
index ea0d32f5396c..53f412f0ca32 100644
--- a/drivers/gpu/nova-core/regs.rs
+++ b/drivers/gpu/nova-core/regs.rs
@@ -364,6 +364,36 @@ pub(crate) fn with_falcon_mem(self, mem: FalconMem) -> Self {
1:1 startcpu as bool;
});
+// IMEM access control register. Up to 4 ports are available for IMEM access.
+register!(NV_PFALCON_FALCON_IMEMC @ PFalconBase[0x00000180[4; 16]] {
+ 15:0 offs as u16, "IMEM block and word offset";
+ 24:24 aincw as bool, "Auto-increment on write";
+ 28:28 secure as bool, "Access secure IMEM";
+});
+
+// IMEM data register. Reading/writing this register accesses IMEM at the address
+// specified by the corresponding IMEMC register.
+register!(NV_PFALCON_FALCON_IMEMD @ PFalconBase[0x00000184[4; 16]] {
+ 31:0 data as u32;
+});
+
+// IMEM tag register. Used to set the tag for the current IMEM block.
+register!(NV_PFALCON_FALCON_IMEMT @ PFalconBase[0x00000188[4; 16]] {
+ 15:0 tag as u16;
+});
+
+// DMEM access control register. Up to 8 ports are available for DMEM access.
+register!(NV_PFALCON_FALCON_DMEMC @ PFalconBase[0x000001c0[8; 8]] {
+ 15:0 offs as u16, "DMEM block and word offset";
+ 24:24 aincw as bool, "Auto-increment on write";
+});
+
+// DMEM data register. Reading/writing this register accesses DMEM at the address
+// specified by the corresponding DMEMC register.
+register!(NV_PFALCON_FALCON_DMEMD @ PFalconBase[0x000001c4[8; 8]] {
+ 31:0 data as u32;
+});
+
// Actually known as `NV_PSEC_FALCON_ENGINE` and `NV_PGSP_FALCON_ENGINE` depending on the falcon
// instance.
register!(NV_PFALCON_FALCON_ENGINE @ PFalconBase[0x000003c0] {
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v11 07/12] gpu: nova-core: falcon: remove unwarranted safety check in dma_load
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (5 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 06/12] gpu: nova-core: add PIO support for loading firmware images Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 08/12] gpu: nova-core: firmware: add comments to justify v3 header values Alexandre Courbot
` (6 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
This safety check was an assumption based on the firmwares we work with
- it is not based on an actual hardware limitation. Thus, remove it.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/falcon.rs | 7 -------
1 file changed, 7 deletions(-)
diff --git a/drivers/gpu/nova-core/falcon.rs b/drivers/gpu/nova-core/falcon.rs
index 2168ef2c5148..7097a206ec3c 100644
--- a/drivers/gpu/nova-core/falcon.rs
+++ b/drivers/gpu/nova-core/falcon.rs
@@ -740,13 +740,6 @@ fn dma_load<F: FalconFirmware<Target = E> + FalconDmaLoadable>(
bar: &Bar0,
fw: &F,
) -> Result {
- // The Non-Secure section only exists on firmware used by Turing and GA100, and
- // those platforms do not use DMA.
- if fw.imem_ns_load_params().is_some() {
- debug_assert!(false);
- return Err(EINVAL);
- }
-
// Create DMA object with firmware content as the source of the DMA engine.
let dma_obj = DmaObject::from_data(dev, fw.as_slice())?;
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v11 08/12] gpu: nova-core: firmware: add comments to justify v3 header values
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (6 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 07/12] gpu: nova-core: falcon: remove unwarranted safety check in dma_load Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-09 4:54 ` Eliot Courtney
2026-03-06 4:52 ` [PATCH v11 09/12] gpu: nova-core: firmware: fix and explain v2 header offsets computations Alexandre Courbot
` (5 subsequent siblings)
13 siblings, 1 reply; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
There is no member in `FalconUCodeDescV3` to describe the start offsets
of the IMEM and DMEM section in the firmware object. Add comments to
justify how they are computed.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/firmware.rs | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
index 677e1dac6d9f..c2b24906fb7e 100644
--- a/drivers/gpu/nova-core/firmware.rs
+++ b/drivers/gpu/nova-core/firmware.rs
@@ -260,6 +260,7 @@ fn signature_versions(&self) -> u16 {
fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
FalconDmaLoadTarget {
+ // IMEM segment always starts at offset 0.
src_start: 0,
dst_start: self.imem_phys_base,
len: self.imem_load_size,
@@ -273,6 +274,7 @@ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
fn dmem_load_params(&self) -> FalconDmaLoadTarget {
FalconDmaLoadTarget {
+ // DMEM segment starts right after the IMEM one.
src_start: self.imem_load_size,
dst_start: self.dmem_phys_base,
len: self.dmem_load_size,
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v11 08/12] gpu: nova-core: firmware: add comments to justify v3 header values
2026-03-06 4:52 ` [PATCH v11 08/12] gpu: nova-core: firmware: add comments to justify v3 header values Alexandre Courbot
@ 2026-03-09 4:54 ` Eliot Courtney
0 siblings, 0 replies; 31+ messages in thread
From: Eliot Courtney @ 2026-03-09 4:54 UTC (permalink / raw)
To: Alexandre Courbot, Danilo Krummrich, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel, dri-devel
On Fri Mar 6, 2026 at 1:52 PM JST, Alexandre Courbot wrote:
> There is no member in `FalconUCodeDescV3` to describe the start offsets
> of the IMEM and DMEM section in the firmware object. Add comments to
> justify how they are computed.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
> drivers/gpu/nova-core/firmware.rs | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
> index 677e1dac6d9f..c2b24906fb7e 100644
> --- a/drivers/gpu/nova-core/firmware.rs
> +++ b/drivers/gpu/nova-core/firmware.rs
> @@ -260,6 +260,7 @@ fn signature_versions(&self) -> u16 {
>
> fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
> FalconDmaLoadTarget {
> + // IMEM segment always starts at offset 0.
> src_start: 0,
> dst_start: self.imem_phys_base,
> len: self.imem_load_size,
> @@ -273,6 +274,7 @@ fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
>
> fn dmem_load_params(&self) -> FalconDmaLoadTarget {
> FalconDmaLoadTarget {
> + // DMEM segment starts right after the IMEM one.
> src_start: self.imem_load_size,
> dst_start: self.dmem_phys_base,
> len: self.dmem_load_size,
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v11 09/12] gpu: nova-core: firmware: fix and explain v2 header offsets computations
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (7 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 08/12] gpu: nova-core: firmware: add comments to justify v3 header values Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-09 4:55 ` Eliot Courtney
2026-03-09 12:10 ` Gary Guo
2026-03-06 4:52 ` [PATCH v11 10/12] gpu: nova-core: make Chipset::arch() const Alexandre Courbot
` (4 subsequent siblings)
13 siblings, 2 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
There are no offsets in `FalconUCodeDescV2` to give the non-secure and
secure IMEM sections start offsets relative to the beginning of the
firmware object.
The start offsets for both sections were set to `0`, but that is
obviously incorrect since two different sections cannot start at the
same offset. Since these offsets were not used by the bootloader, this
doesn't prevent proper function but is incorrect nonetheless.
Fix this by computing the start of the secure IMEM section relatively to
the start of the firmware object and setting it properly. Also add and
improve comments to explain how the values are obtained.
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/firmware.rs | 16 ++++++++++++----
1 file changed, 12 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
index c2b24906fb7e..5e56c09cc2df 100644
--- a/drivers/gpu/nova-core/firmware.rs
+++ b/drivers/gpu/nova-core/firmware.rs
@@ -63,7 +63,8 @@ pub(crate) struct FalconUCodeDescV2 {
pub(crate) interface_offset: u32,
/// Base address at which to load the code segment into 'IMEM'.
pub(crate) imem_phys_base: u32,
- /// Size in bytes of the code to copy into 'IMEM'.
+ /// Size in bytes of the code to copy into 'IMEM' (includes both secure and non-secure
+ /// segments).
pub(crate) imem_load_size: u32,
/// Virtual 'IMEM' address (i.e. 'tag') at which the code should start.
pub(crate) imem_virt_base: u32,
@@ -205,18 +206,25 @@ fn signature_versions(&self) -> u16 {
}
fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
+ // `imem_sec_base` is the *virtual* start address of the secure IMEM segment, so subtract
+ // `imem_virt_base` to get its physical offset.
+ let imem_sec_start = self.imem_sec_base.saturating_sub(self.imem_virt_base);
+
FalconDmaLoadTarget {
- src_start: 0,
- dst_start: self.imem_sec_base,
+ src_start: imem_sec_start,
+ dst_start: self.imem_phys_base.saturating_add(imem_sec_start),
len: self.imem_sec_size,
}
}
fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
Some(FalconDmaLoadTarget {
+ // Non-secure code always starts at offset 0.
src_start: 0,
dst_start: self.imem_phys_base,
- len: self.imem_load_size.checked_sub(self.imem_sec_size)?,
+ // `imem_load_size` includes the size of the secure segment, so subtract it to
+ // get the correct amount of data to copy.
+ len: self.imem_load_size.saturating_sub(self.imem_sec_size),
})
}
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v11 09/12] gpu: nova-core: firmware: fix and explain v2 header offsets computations
2026-03-06 4:52 ` [PATCH v11 09/12] gpu: nova-core: firmware: fix and explain v2 header offsets computations Alexandre Courbot
@ 2026-03-09 4:55 ` Eliot Courtney
2026-03-09 12:10 ` Gary Guo
1 sibling, 0 replies; 31+ messages in thread
From: Eliot Courtney @ 2026-03-09 4:55 UTC (permalink / raw)
To: Alexandre Courbot, Danilo Krummrich, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel, dri-devel
On Fri Mar 6, 2026 at 1:52 PM JST, Alexandre Courbot wrote:
> There are no offsets in `FalconUCodeDescV2` to give the non-secure and
> secure IMEM sections start offsets relative to the beginning of the
> firmware object.
>
> The start offsets for both sections were set to `0`, but that is
> obviously incorrect since two different sections cannot start at the
> same offset. Since these offsets were not used by the bootloader, this
> doesn't prevent proper function but is incorrect nonetheless.
>
> Fix this by computing the start of the secure IMEM section relatively to
> the start of the firmware object and setting it properly. Also add and
> improve comments to explain how the values are obtained.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 09/12] gpu: nova-core: firmware: fix and explain v2 header offsets computations
2026-03-06 4:52 ` [PATCH v11 09/12] gpu: nova-core: firmware: fix and explain v2 header offsets computations Alexandre Courbot
2026-03-09 4:55 ` Eliot Courtney
@ 2026-03-09 12:10 ` Gary Guo
2026-03-10 1:49 ` Alexandre Courbot
1 sibling, 1 reply; 31+ messages in thread
From: Gary Guo @ 2026-03-09 12:10 UTC (permalink / raw)
To: Alexandre Courbot, Danilo Krummrich, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
On Fri Mar 6, 2026 at 4:52 AM GMT, Alexandre Courbot wrote:
> There are no offsets in `FalconUCodeDescV2` to give the non-secure and
> secure IMEM sections start offsets relative to the beginning of the
> firmware object.
>
> The start offsets for both sections were set to `0`, but that is
> obviously incorrect since two different sections cannot start at the
> same offset. Since these offsets were not used by the bootloader, this
> doesn't prevent proper function but is incorrect nonetheless.
>
> Fix this by computing the start of the secure IMEM section relatively to
> the start of the firmware object and setting it properly. Also add and
> improve comments to explain how the values are obtained.
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
> ---
> drivers/gpu/nova-core/firmware.rs | 16 ++++++++++++----
> 1 file changed, 12 insertions(+), 4 deletions(-)
>
> diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
> index c2b24906fb7e..5e56c09cc2df 100644
> --- a/drivers/gpu/nova-core/firmware.rs
> +++ b/drivers/gpu/nova-core/firmware.rs
> @@ -63,7 +63,8 @@ pub(crate) struct FalconUCodeDescV2 {
> pub(crate) interface_offset: u32,
> /// Base address at which to load the code segment into 'IMEM'.
> pub(crate) imem_phys_base: u32,
> - /// Size in bytes of the code to copy into 'IMEM'.
> + /// Size in bytes of the code to copy into 'IMEM' (includes both secure and non-secure
> + /// segments).
> pub(crate) imem_load_size: u32,
> /// Virtual 'IMEM' address (i.e. 'tag') at which the code should start.
> pub(crate) imem_virt_base: u32,
> @@ -205,18 +206,25 @@ fn signature_versions(&self) -> u16 {
> }
>
> fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
> + // `imem_sec_base` is the *virtual* start address of the secure IMEM segment, so subtract
> + // `imem_virt_base` to get its physical offset.
> + let imem_sec_start = self.imem_sec_base.saturating_sub(self.imem_virt_base);
Why is saturating sub used here? I didn't see any explaination on why the
saturating semantics is preferred over checked ones.
Best,
Gary
> +
> FalconDmaLoadTarget {
> - src_start: 0,
> - dst_start: self.imem_sec_base,
> + src_start: imem_sec_start,
> + dst_start: self.imem_phys_base.saturating_add(imem_sec_start),
> len: self.imem_sec_size,
> }
> }
>
> fn imem_ns_load_params(&self) -> Option<FalconDmaLoadTarget> {
> Some(FalconDmaLoadTarget {
> + // Non-secure code always starts at offset 0.
> src_start: 0,
> dst_start: self.imem_phys_base,
> - len: self.imem_load_size.checked_sub(self.imem_sec_size)?,
> + // `imem_load_size` includes the size of the secure segment, so subtract it to
> + // get the correct amount of data to copy.
> + len: self.imem_load_size.saturating_sub(self.imem_sec_size),
> })
> }
>
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v11 09/12] gpu: nova-core: firmware: fix and explain v2 header offsets computations
2026-03-09 12:10 ` Gary Guo
@ 2026-03-10 1:49 ` Alexandre Courbot
0 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-10 1:49 UTC (permalink / raw)
To: Gary Guo
Cc: Danilo Krummrich, Alice Ryhl, David Airlie, Simona Vetter,
John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
On Mon Mar 9, 2026 at 9:10 PM JST, Gary Guo wrote:
> On Fri Mar 6, 2026 at 4:52 AM GMT, Alexandre Courbot wrote:
>> There are no offsets in `FalconUCodeDescV2` to give the non-secure and
>> secure IMEM sections start offsets relative to the beginning of the
>> firmware object.
>>
>> The start offsets for both sections were set to `0`, but that is
>> obviously incorrect since two different sections cannot start at the
>> same offset. Since these offsets were not used by the bootloader, this
>> doesn't prevent proper function but is incorrect nonetheless.
>>
>> Fix this by computing the start of the secure IMEM section relatively to
>> the start of the firmware object and setting it properly. Also add and
>> improve comments to explain how the values are obtained.
>>
>> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>> ---
>> drivers/gpu/nova-core/firmware.rs | 16 ++++++++++++----
>> 1 file changed, 12 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
>> index c2b24906fb7e..5e56c09cc2df 100644
>> --- a/drivers/gpu/nova-core/firmware.rs
>> +++ b/drivers/gpu/nova-core/firmware.rs
>> @@ -63,7 +63,8 @@ pub(crate) struct FalconUCodeDescV2 {
>> pub(crate) interface_offset: u32,
>> /// Base address at which to load the code segment into 'IMEM'.
>> pub(crate) imem_phys_base: u32,
>> - /// Size in bytes of the code to copy into 'IMEM'.
>> + /// Size in bytes of the code to copy into 'IMEM' (includes both secure and non-secure
>> + /// segments).
>> pub(crate) imem_load_size: u32,
>> /// Virtual 'IMEM' address (i.e. 'tag') at which the code should start.
>> pub(crate) imem_virt_base: u32,
>> @@ -205,18 +206,25 @@ fn signature_versions(&self) -> u16 {
>> }
>>
>> fn imem_sec_load_params(&self) -> FalconDmaLoadTarget {
>> + // `imem_sec_base` is the *virtual* start address of the secure IMEM segment, so subtract
>> + // `imem_virt_base` to get its physical offset.
>> + let imem_sec_start = self.imem_sec_base.saturating_sub(self.imem_virt_base);
>
> Why is saturating sub used here? I didn't see any explaination on why the
> saturating semantics is preferred over checked ones.
They let us keep this method infallible, and an incorrect value here
will just result in the firmware not booting.
But, maybe we could compute this value at construction time with a
checked operation and return an error there. Actually that would
probably be better. I'll see if I can follow-up with a fix for that.
^ permalink raw reply [flat|nested] 31+ messages in thread
* [PATCH v11 10/12] gpu: nova-core: make Chipset::arch() const
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (8 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 09/12] gpu: nova-core: firmware: fix and explain v2 header offsets computations Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 11/12] gpu: nova-core: add gen_bootloader firmware to ModInfoBuilder Alexandre Courbot
` (3 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
We will use this method from const context.
Also take `self` by value since it is the size of a primitive type and
implements `Copy`.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/gpu.rs | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index 60c85fffaeaf..c14d411c6759 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -92,7 +92,7 @@ fn try_from(value: u32) -> Result<Self, Self::Error> {
});
impl Chipset {
- pub(crate) fn arch(&self) -> Architecture {
+ pub(crate) const fn arch(self) -> Architecture {
match self {
Self::TU102 | Self::TU104 | Self::TU106 | Self::TU117 | Self::TU116 => {
Architecture::Turing
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v11 11/12] gpu: nova-core: add gen_bootloader firmware to ModInfoBuilder
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (9 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 10/12] gpu: nova-core: make Chipset::arch() const Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-06 4:52 ` [PATCH v11 12/12] gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing Alexandre Courbot
` (2 subsequent siblings)
13 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
Turing GPUs need an additional firmware file (the FWSEC generic
bootloader) in order to initialize. Add it to `ModInfoBuilder`.
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/firmware.rs | 21 +++++++++++++++------
drivers/gpu/nova-core/gpu.rs | 7 +++++++
2 files changed, 22 insertions(+), 6 deletions(-)
diff --git a/drivers/gpu/nova-core/firmware.rs b/drivers/gpu/nova-core/firmware.rs
index 5e56c09cc2df..6bd203c94b27 100644
--- a/drivers/gpu/nova-core/firmware.rs
+++ b/drivers/gpu/nova-core/firmware.rs
@@ -425,11 +425,20 @@ const fn make_entry_file(self, chipset: &str, fw: &str) -> Self {
)
}
- const fn make_entry_chipset(self, chipset: &str) -> Self {
- self.make_entry_file(chipset, "booter_load")
- .make_entry_file(chipset, "booter_unload")
- .make_entry_file(chipset, "bootloader")
- .make_entry_file(chipset, "gsp")
+ const fn make_entry_chipset(self, chipset: gpu::Chipset) -> Self {
+ let name = chipset.name();
+
+ let this = self
+ .make_entry_file(name, "booter_load")
+ .make_entry_file(name, "booter_unload")
+ .make_entry_file(name, "bootloader")
+ .make_entry_file(name, "gsp");
+
+ if chipset.needs_fwsec_bootloader() {
+ this.make_entry_file(name, "gen_bootloader")
+ } else {
+ this
+ }
}
pub(crate) const fn create(
@@ -439,7 +448,7 @@ pub(crate) const fn create(
let mut i = 0;
while i < gpu::Chipset::ALL.len() {
- this = this.make_entry_chipset(gpu::Chipset::ALL[i].name());
+ this = this.make_entry_chipset(gpu::Chipset::ALL[i]);
i += 1;
}
diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs
index c14d411c6759..8579d632e717 100644
--- a/drivers/gpu/nova-core/gpu.rs
+++ b/drivers/gpu/nova-core/gpu.rs
@@ -105,6 +105,13 @@ pub(crate) const fn arch(self) -> Architecture {
}
}
}
+
+ /// Returns `true` if this chipset requires the PIO-loaded bootloader in order to boot FWSEC.
+ ///
+ /// This includes all chipsets < GA102.
+ pub(crate) const fn needs_fwsec_bootloader(self) -> bool {
+ matches!(self.arch(), Architecture::Turing) || matches!(self, Self::GA100)
+ }
}
// TODO
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* [PATCH v11 12/12] gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (10 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 11/12] gpu: nova-core: add gen_bootloader firmware to ModInfoBuilder Alexandre Courbot
@ 2026-03-06 4:52 ` Alexandre Courbot
2026-03-09 5:07 ` Eliot Courtney
2026-03-09 1:52 ` [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
2026-03-09 19:48 ` Ewan Chorynski
13 siblings, 1 reply; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-06 4:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
From: Timur Tabi <ttabi@nvidia.com>
On Turing and GA100, a new firmware image called the Generic Bootloader
(gen_bootloader) must be used to load FWSEC into Falcon memory. The
driver loads the generic bootloader into Falcon IMEM, passes a
descriptor that points to FWSEC using DMEM, and then boots the generic
bootloader. The bootloader will then load FWSEC into IMEM and boot it.
Signed-off-by: Timur Tabi <ttabi@nvidia.com>
Co-developed-by: Alexandre Courbot <acourbot@nvidia.com>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
drivers/gpu/nova-core/firmware/fwsec.rs | 6 +
drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 348 +++++++++++++++++++++
drivers/gpu/nova-core/gsp/boot.rs | 15 +-
3 files changed, 366 insertions(+), 3 deletions(-)
diff --git a/drivers/gpu/nova-core/firmware/fwsec.rs b/drivers/gpu/nova-core/firmware/fwsec.rs
index 87495d1d6cac..fb2bb14b9b33 100644
--- a/drivers/gpu/nova-core/firmware/fwsec.rs
+++ b/drivers/gpu/nova-core/firmware/fwsec.rs
@@ -10,6 +10,8 @@
//! - The command to be run, as this firmware can perform several tasks ;
//! - The ucode signature, so the GSP falcon can run FWSEC in HS mode.
+pub(crate) mod bootloader;
+
use core::marker::PhantomData;
use kernel::{
@@ -385,6 +387,10 @@ pub(crate) fn new(
}
/// Loads the FWSEC firmware into `falcon` and execute it.
+ ///
+ /// This must only be called on chipsets that do not need the FWSEC bootloader (i.e., where
+ /// [`Chipset::needs_fwsec_bootloader()`](crate::gpu::Chipset::needs_fwsec_bootloader) returns
+ /// `false`). On chipsets that do, use [`bootloader::FwsecFirmwareWithBl`] instead.
pub(crate) fn run(
&self,
dev: &Device<device::Bound>,
diff --git a/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs
new file mode 100644
index 000000000000..b106bae170ca
--- /dev/null
+++ b/drivers/gpu/nova-core/firmware/fwsec/bootloader.rs
@@ -0,0 +1,348 @@
+// SPDX-License-Identifier: GPL-2.0
+
+//! Bootloader support for the FWSEC firmware.
+//!
+//! On Turing, the FWSEC firmware is not loaded directly, but is instead loaded through a small
+//! bootloader program that performs the required DMA operations. This bootloader itself needs to
+//! be loaded using PIO.
+
+use kernel::{
+ alloc::KVec,
+ device::{
+ self,
+ Device, //
+ },
+ prelude::*,
+ ptr::{
+ Alignable,
+ Alignment, //
+ },
+ sizes,
+ transmute::{
+ AsBytes,
+ FromBytes, //
+ },
+};
+
+use crate::{
+ dma::DmaObject,
+ driver::Bar0,
+ falcon::{
+ self,
+ gsp::Gsp,
+ Falcon,
+ FalconBromParams,
+ FalconDmaLoadable,
+ FalconEngine,
+ FalconFbifMemType,
+ FalconFbifTarget,
+ FalconFirmware,
+ FalconPioDmemLoadTarget,
+ FalconPioImemLoadTarget,
+ FalconPioLoadable, //
+ },
+ firmware::{
+ fwsec::FwsecFirmware,
+ request_firmware,
+ BinHdr,
+ FIRMWARE_VERSION, //
+ },
+ gpu::Chipset,
+ num::FromSafeCast,
+ regs,
+};
+
+/// Descriptor used by RM to figure out the requirements of the boot loader.
+///
+/// Most of its fields appear to be legacy and carry incorrect values, so they are left unused.
+#[repr(C)]
+#[derive(Debug, Clone)]
+struct BootloaderDesc {
+ /// Starting tag of bootloader.
+ start_tag: u32,
+ /// DMEM load offset - unused here as we always load at offset `0`.
+ _dmem_load_off: u32,
+ /// Offset of code section in the image. Unused as there is only one section in the bootloader
+ /// binary.
+ _code_off: u32,
+ /// Size of code section in the image.
+ code_size: u32,
+ /// Offset of data section in the image. Unused as we build the data section ourselves.
+ _data_off: u32,
+ /// Size of data section in the image. Unused as we build the data section ourselves.
+ _data_size: u32,
+}
+// SAFETY: any byte sequence is valid for this struct.
+unsafe impl FromBytes for BootloaderDesc {}
+
+/// Structure used by the boot-loader to load the rest of the code.
+///
+/// This has to be filled by the GPU driver and copied into DMEM at offset
+/// [`BootloaderDesc.dmem_load_off`].
+#[repr(C, packed)]
+#[derive(Debug, Clone)]
+struct BootloaderDmemDescV2 {
+ /// Reserved, should always be first element.
+ reserved: [u32; 4],
+ /// 16B signature for secure code, 0s if no secure code.
+ signature: [u32; 4],
+ /// DMA context used by the bootloader while loading code/data.
+ ctx_dma: u32,
+ /// 256B-aligned physical FB address where code is located.
+ code_dma_base: u64,
+ /// Offset from `code_dma_base` where the non-secure code is located.
+ ///
+ /// Also used as destination IMEM offset of non-secure code as the DMA firmware object is
+ /// expected to be a mirror image of its loaded state.
+ ///
+ /// Must be multiple of 256.
+ non_sec_code_off: u32,
+ /// Size of the non-secure code part.
+ non_sec_code_size: u32,
+ /// Offset from `code_dma_base` where the secure code is located (must be multiple of 256).
+ ///
+ /// Also used as destination IMEM offset of secure code as the DMA firmware object is expected
+ /// to be a mirror image of its loaded state.
+ ///
+ /// Must be multiple of 256.
+ sec_code_off: u32,
+ /// Size of the secure code part.
+ sec_code_size: u32,
+ /// Code entry point invoked by the bootloader after code is loaded.
+ code_entry_point: u32,
+ /// 256B-aligned physical FB address where data is located.
+ data_dma_base: u64,
+ /// Size of data block (should be multiple of 256B).
+ data_size: u32,
+ /// Number of arguments to be passed to the target firmware being loaded.
+ argc: u32,
+ /// Arguments to be passed to the target firmware being loaded.
+ argv: u32,
+}
+// SAFETY: This struct doesn't contain uninitialized bytes and doesn't have interior mutability.
+unsafe impl AsBytes for BootloaderDmemDescV2 {}
+
+/// Wrapper for [`FwsecFirmware`] that includes the bootloader performing the actual load
+/// operation.
+pub(crate) struct FwsecFirmwareWithBl {
+ /// DMA object the bootloader will copy the firmware from.
+ _firmware_dma: DmaObject,
+ /// Code of the bootloader to be loaded into non-secure IMEM.
+ ucode: KVec<u8>,
+ /// Descriptor to be loaded into DMEM for the bootloader to read.
+ dmem_desc: BootloaderDmemDescV2,
+ /// Range-validated start offset of the firmware code in IMEM.
+ imem_dst_start: u16,
+ /// BROM parameters of the loaded firmware.
+ brom_params: FalconBromParams,
+ /// Range-validated `desc.start_tag`.
+ start_tag: u16,
+}
+
+impl FwsecFirmwareWithBl {
+ /// Loads the bootloader firmware for `dev` and `chipset`, and wrap `firmware` so it can be
+ /// loaded using it.
+ pub(crate) fn new(
+ firmware: FwsecFirmware,
+ dev: &Device<device::Bound>,
+ chipset: Chipset,
+ ) -> Result<Self> {
+ let fw = request_firmware(dev, chipset, "gen_bootloader", FIRMWARE_VERSION)?;
+ let hdr = fw
+ .data()
+ .get(0..size_of::<BinHdr>())
+ .and_then(BinHdr::from_bytes_copy)
+ .ok_or(EINVAL)?;
+
+ let desc = {
+ let desc_offset = usize::from_safe_cast(hdr.header_offset);
+
+ fw.data()
+ .get(desc_offset..)
+ .and_then(BootloaderDesc::from_bytes_copy_prefix)
+ .ok_or(EINVAL)?
+ .0
+ };
+
+ let ucode = {
+ let ucode_start = usize::from_safe_cast(hdr.data_offset);
+ let code_size = usize::from_safe_cast(desc.code_size);
+ // Align to falcon block size (256 bytes).
+ let aligned_code_size = code_size
+ .align_up(Alignment::new::<{ falcon::MEM_BLOCK_ALIGNMENT }>())
+ .ok_or(EINVAL)?;
+
+ let mut ucode = KVec::with_capacity(aligned_code_size, GFP_KERNEL)?;
+ ucode.extend_from_slice(
+ fw.data()
+ .get(ucode_start..ucode_start + code_size)
+ .ok_or(EINVAL)?,
+ GFP_KERNEL,
+ )?;
+ ucode.resize(aligned_code_size, 0, GFP_KERNEL)?;
+
+ ucode
+ };
+
+ // `BootloaderDmemDescV2` expects the source to be a mirror image of the destination
+ // and uses the same offset parameter for both.
+ //
+ // Thus, the start of the source object needs to be padded with the difference betwen
+ // the destination and source offsets.
+ //
+ // In practice, this is expected to always be zero but is required for code
+ // correctness.
+ let (align_padding, firmware_dma) = {
+ let align_padding = {
+ let imem_sec = firmware.imem_sec_load_params();
+
+ imem_sec
+ .dst_start
+ .checked_sub(imem_sec.src_start)
+ .map(usize::from_safe_cast)
+ .ok_or(EOVERFLOW)?
+ };
+
+ let mut firmware_obj = KVVec::new();
+ firmware_obj.extend_with(align_padding, 0u8, GFP_KERNEL)?;
+ firmware_obj.extend_from_slice(firmware.ucode.0.as_slice(), GFP_KERNEL)?;
+
+ (
+ align_padding,
+ DmaObject::from_data(dev, firmware_obj.as_slice())?,
+ )
+ };
+
+ let dmem_desc = {
+ // Bootloader payload is in non-coherent system memory.
+ const FALCON_DMAIDX_PHYS_SYS_NCOH: u32 = 4;
+
+ let imem_sec = firmware.imem_sec_load_params();
+ let imem_ns = firmware.imem_ns_load_params().ok_or(EINVAL)?;
+ let dmem = firmware.dmem_load_params();
+
+ // The bootloader does not have a data destination offset field and copies the data at
+ // the start of DMEM, so it can only be used if the destination offset of the firmware
+ // is 0.
+ if dmem.dst_start != 0 {
+ return Err(EINVAL);
+ }
+
+ BootloaderDmemDescV2 {
+ reserved: [0; 4],
+ signature: [0; 4],
+ ctx_dma: FALCON_DMAIDX_PHYS_SYS_NCOH,
+ code_dma_base: firmware_dma.dma_handle(),
+ // `dst_start` is also valid as the source offset since the firmware DMA object is
+ // a mirror image of the target IMEM layout.
+ non_sec_code_off: imem_ns.dst_start,
+ non_sec_code_size: imem_ns.len,
+ // `dst_start` is also valid as the source offset since the firmware DMA object is
+ // a mirror image of the target IMEM layout.
+ sec_code_off: imem_sec.dst_start,
+ sec_code_size: imem_sec.len,
+ code_entry_point: 0,
+ // Start of data section is the added padding + the DMEM `src_start` field.
+ data_dma_base: firmware_dma
+ .dma_handle()
+ .checked_add(u64::from_safe_cast(align_padding))
+ .and_then(|offset| offset.checked_add(dmem.src_start.into()))
+ .ok_or(EOVERFLOW)?,
+ data_size: dmem.len,
+ argc: 0,
+ argv: 0,
+ }
+ };
+
+ // The bootloader's code must be loaded in the area right below the first 64K of IMEM.
+ const BOOTLOADER_LOAD_CEILING: usize = sizes::SZ_64K;
+ let imem_dst_start = BOOTLOADER_LOAD_CEILING
+ .checked_sub(ucode.len())
+ .ok_or(EOVERFLOW)?;
+
+ Ok(Self {
+ _firmware_dma: firmware_dma,
+ ucode,
+ dmem_desc,
+ brom_params: firmware.brom_params(),
+ imem_dst_start: u16::try_from(imem_dst_start)?,
+ start_tag: u16::try_from(desc.start_tag)?,
+ })
+ }
+
+ /// Loads the bootloader into `falcon` and execute it.
+ ///
+ /// The bootloader will load the FWSEC firmware and then execute it. This function returns
+ /// after FWSEC has reached completion.
+ pub(crate) fn run(
+ &self,
+ dev: &Device<device::Bound>,
+ falcon: &Falcon<Gsp>,
+ bar: &Bar0,
+ ) -> Result<()> {
+ // Reset falcon, load the firmware, and run it.
+ falcon
+ .reset(bar)
+ .inspect_err(|e| dev_err!(dev, "Failed to reset GSP falcon: {:?}\n", e))?;
+ falcon
+ .pio_load(bar, self)
+ .inspect_err(|e| dev_err!(dev, "Failed to load FWSEC firmware: {:?}\n", e))?;
+
+ // Configure DMA index for the bootloader to fetch the FWSEC firmware from system memory.
+ regs::NV_PFALCON_FBIF_TRANSCFG::try_update(
+ bar,
+ &Gsp::ID,
+ usize::from_safe_cast(self.dmem_desc.ctx_dma),
+ |v| {
+ v.set_target(FalconFbifTarget::CoherentSysmem)
+ .set_mem_type(FalconFbifMemType::Physical)
+ },
+ )?;
+
+ let (mbox0, _) = falcon
+ .boot(bar, Some(0), None)
+ .inspect_err(|e| dev_err!(dev, "Failed to boot FWSEC firmware: {:?}\n", e))?;
+ if mbox0 != 0 {
+ dev_err!(dev, "FWSEC firmware returned error {}\n", mbox0);
+ Err(EIO)
+ } else {
+ Ok(())
+ }
+ }
+}
+
+impl FalconFirmware for FwsecFirmwareWithBl {
+ type Target = Gsp;
+
+ fn brom_params(&self) -> FalconBromParams {
+ self.brom_params.clone()
+ }
+
+ fn boot_addr(&self) -> u32 {
+ // On V2 platforms, the boot address is extracted from the generic bootloader, because the
+ // gbl is what actually copies FWSEC into memory, so that is what needs to be booted.
+ u32::from(self.start_tag) << 8
+ }
+}
+
+impl FalconPioLoadable for FwsecFirmwareWithBl {
+ fn imem_sec_load_params(&self) -> Option<FalconPioImemLoadTarget<'_>> {
+ None
+ }
+
+ fn imem_ns_load_params(&self) -> Option<FalconPioImemLoadTarget<'_>> {
+ Some(FalconPioImemLoadTarget {
+ data: self.ucode.as_ref(),
+ dst_start: self.imem_dst_start,
+ secure: false,
+ start_tag: self.start_tag,
+ })
+ }
+
+ fn dmem_load_params(&self) -> FalconPioDmemLoadTarget<'_> {
+ FalconPioDmemLoadTarget {
+ data: self.dmem_desc.as_bytes(),
+ dst_start: 0,
+ }
+ }
+}
diff --git a/drivers/gpu/nova-core/gsp/boot.rs b/drivers/gpu/nova-core/gsp/boot.rs
index 78957ed8814f..9a00ddb922ac 100644
--- a/drivers/gpu/nova-core/gsp/boot.rs
+++ b/drivers/gpu/nova-core/gsp/boot.rs
@@ -24,6 +24,7 @@
BooterKind, //
},
fwsec::{
+ bootloader::FwsecFirmwareWithBl,
FwsecCommand,
FwsecFirmware, //
},
@@ -48,6 +49,7 @@ impl super::Gsp {
/// created the WPR2 region.
fn run_fwsec_frts(
dev: &device::Device<device::Bound>,
+ chipset: Chipset,
falcon: &Falcon<Gsp>,
bar: &Bar0,
bios: &Vbios,
@@ -63,6 +65,7 @@ fn run_fwsec_frts(
return Err(EBUSY);
}
+ // FWSEC-FRTS will create the WPR2 region.
let fwsec_frts = FwsecFirmware::new(
dev,
falcon,
@@ -74,8 +77,14 @@ fn run_fwsec_frts(
},
)?;
- // Run FWSEC-FRTS to create the WPR2 region.
- fwsec_frts.run(dev, falcon, bar)?;
+ if chipset.needs_fwsec_bootloader() {
+ let fwsec_frts_bl = FwsecFirmwareWithBl::new(fwsec_frts, dev, chipset)?;
+ // Load and run the bootloader, which will load FWSEC-FRTS and run it.
+ fwsec_frts_bl.run(dev, falcon, bar)?;
+ } else {
+ // Load and run FWSEC-FRTS directly.
+ fwsec_frts.run(dev, falcon, bar)?;
+ }
// SCRATCH_E contains the error code for FWSEC-FRTS.
let frts_status = regs::NV_PBUS_SW_SCRATCH_0E_FRTS_ERR::read(bar).frts_err_code();
@@ -144,7 +153,7 @@ pub(crate) fn boot(
let fb_layout = FbLayout::new(chipset, bar, &gsp_fw)?;
dev_dbg!(dev, "{:#x?}\n", fb_layout);
- Self::run_fwsec_frts(dev, gsp_falcon, bar, &bios, &fb_layout)?;
+ Self::run_fwsec_frts(dev, chipset, gsp_falcon, bar, &bios, &fb_layout)?;
let booter_loader = BooterFirmware::new(
dev,
--
2.53.0
^ permalink raw reply related [flat|nested] 31+ messages in thread* Re: [PATCH v11 12/12] gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing
2026-03-06 4:52 ` [PATCH v11 12/12] gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing Alexandre Courbot
@ 2026-03-09 5:07 ` Eliot Courtney
0 siblings, 0 replies; 31+ messages in thread
From: Eliot Courtney @ 2026-03-09 5:07 UTC (permalink / raw)
To: Alexandre Courbot, Danilo Krummrich, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel, dri-devel
On Fri Mar 6, 2026 at 1:52 PM JST, Alexandre Courbot wrote:
> +/// Descriptor used by RM to figure out the requirements of the boot loader.
> +///
> +/// Most of its fields appear to be legacy and carry incorrect values, so they are left unused.
> +#[repr(C)]
> +#[derive(Debug, Clone)]
> +struct BootloaderDesc {
> + /// Starting tag of bootloader.
> + start_tag: u32,
> + /// DMEM load offset - unused here as we always load at offset `0`.
> + _dmem_load_off: u32,
> + /// Offset of code section in the image. Unused as there is only one section in the bootloader
> + /// binary.
> + _code_off: u32,
I still think it would be slightly better to use this value, I posted
some more context here:
https://lore.kernel.org/all/DGXZCHSH4JPB.1ZZW2B72MHCMT@nvidia.com/
> + // `BootloaderDmemDescV2` expects the source to be a mirror image of the destination
> + // and uses the same offset parameter for both.
> + //
> + // Thus, the start of the source object needs to be padded with the difference betwen
> + // the destination and source offsets.
> + //
> + // In practice, this is expected to always be zero but is required for code
> + // correctness.
> + let (align_padding, firmware_dma) = {
> + let align_padding = {
> + let imem_sec = firmware.imem_sec_load_params();
> +
> + imem_sec
> + .dst_start
> + .checked_sub(imem_sec.src_start)
> + .map(usize::from_safe_cast)
> + .ok_or(EOVERFLOW)?
> + };
> +
> + let mut firmware_obj = KVVec::new();
> + firmware_obj.extend_with(align_padding, 0u8, GFP_KERNEL)?;
> + firmware_obj.extend_from_slice(firmware.ucode.0.as_slice(), GFP_KERNEL)?;
> +
> + (
> + align_padding,
> + DmaObject::from_data(dev, firmware_obj.as_slice())?,
> + )
> + };
> +
> + let dmem_desc = {
> + // Bootloader payload is in non-coherent system memory.
> + const FALCON_DMAIDX_PHYS_SYS_NCOH: u32 = 4;
> +
> + let imem_sec = firmware.imem_sec_load_params();
> + let imem_ns = firmware.imem_ns_load_params().ok_or(EINVAL)?;
> + let dmem = firmware.dmem_load_params();
> +
> + // The bootloader does not have a data destination offset field and copies the data at
> + // the start of DMEM, so it can only be used if the destination offset of the firmware
> + // is 0.
> + if dmem.dst_start != 0 {
> + return Err(EINVAL);
> + }
> +
> + BootloaderDmemDescV2 {
> + reserved: [0; 4],
> + signature: [0; 4],
> + ctx_dma: FALCON_DMAIDX_PHYS_SYS_NCOH,
> + code_dma_base: firmware_dma.dma_handle(),
> + // `dst_start` is also valid as the source offset since the firmware DMA object is
> + // a mirror image of the target IMEM layout.
> + non_sec_code_off: imem_ns.dst_start,
> + non_sec_code_size: imem_ns.len,
> + // `dst_start` is also valid as the source offset since the firmware DMA object is
> + // a mirror image of the target IMEM layout.
> + sec_code_off: imem_sec.dst_start,
nit: it's incorrect to use `src_start` but the comment implies that it
would also be ok to use `src_start` "is also valid". IIUC we create the padded
firmware above (good catch on finding that!) and that uses `src_start`,
then since the falcon expects the same layout between the source
constructed image and the destination in its memory, it uses these
*_off values doubly to compute the source and destination addresses.
The aligning above is a way to make sure that `dst_start` can properly
perform this double duty. Some comment explaining this might be useful,
IMO.
Apart from that,
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (11 preceding siblings ...)
2026-03-06 4:52 ` [PATCH v11 12/12] gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing Alexandre Courbot
@ 2026-03-09 1:52 ` Alexandre Courbot
2026-03-09 2:06 ` John Hubbard
2026-03-09 19:48 ` Ewan Chorynski
13 siblings, 1 reply; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-09 1:52 UTC (permalink / raw)
To: Danilo Krummrich, Alexandre Courbot, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
On Fri Mar 6, 2026 at 1:52 PM JST, Alexandre Courbot wrote:
> gpu: nova-core: create falcon firmware DMA objects lazily
[acourbot@nvidia.com: add TODO item to switch back to a coherent
allocation when it becomes convenient to do so.]
> gpu: nova-core: falcon: add constant for memory block alignment
> gpu: nova-core: falcon: rename load parameters to reflect DMA dependency
[acourbot@nvidia.com: fixup order of import items.]
> gpu: nova-core: falcon: remove FalconFirmware's dependency on FalconDmaLoadable
> gpu: nova-core: move brom_params and boot_addr to FalconFirmware
> gpu: nova-core: falcon: remove unwarranted safety check in dma_load
> gpu: nova-core: make Chipset::arch() const
> gpu: nova-core: add gen_bootloader firmware to ModInfoBuilder
> gpu: nova-core: add PIO support for loading firmware images
> gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing
All the above pushed to drm-rust-next, thanks!
> gpu: nova-core: firmware: add comments to justify v3 header values
> gpu: nova-core: firmware: fix and explain v2 header offsets computations
These two not pushed yet as they were introduced late and are still
pending proper review.
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 1:52 ` [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
@ 2026-03-09 2:06 ` John Hubbard
2026-03-09 2:20 ` Alexandre Courbot
0 siblings, 1 reply; 31+ messages in thread
From: John Hubbard @ 2026-03-09 2:06 UTC (permalink / raw)
To: Alexandre Courbot, Danilo Krummrich, Alice Ryhl, David Airlie,
Simona Vetter
Cc: Alistair Popple, Joel Fernandes, Timur Tabi, Edwin Peer,
Eliot Courtney, nouveau, rust-for-linux, dri-devel, linux-kernel
On 3/8/26 6:52 PM, Alexandre Courbot wrote:
> On Fri Mar 6, 2026 at 1:52 PM JST, Alexandre Courbot wrote:
>> gpu: nova-core: create falcon firmware DMA objects lazily
> [acourbot@nvidia.com: add TODO item to switch back to a coherent
> allocation when it becomes convenient to do so.]
>> gpu: nova-core: falcon: add constant for memory block alignment
>> gpu: nova-core: falcon: rename load parameters to reflect DMA dependency
> [acourbot@nvidia.com: fixup order of import items.]
>> gpu: nova-core: falcon: remove FalconFirmware's dependency on FalconDmaLoadable
>> gpu: nova-core: move brom_params and boot_addr to FalconFirmware
>> gpu: nova-core: falcon: remove unwarranted safety check in dma_load
>> gpu: nova-core: make Chipset::arch() const
>> gpu: nova-core: add gen_bootloader firmware to ModInfoBuilder
>> gpu: nova-core: add PIO support for loading firmware images
>> gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing
>
> All the above pushed to drm-rust-next, thanks!
>
Amazing! I'll start testing on Turing locally, in addition to Blackwell
and Ampere, now. Exciting!
Congratulations to Timur Tabi, and all of the expert reviewers and
refactor-ers to!
thanks,
--
John Hubbard
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 2:06 ` John Hubbard
@ 2026-03-09 2:20 ` Alexandre Courbot
0 siblings, 0 replies; 31+ messages in thread
From: Alexandre Courbot @ 2026-03-09 2:20 UTC (permalink / raw)
To: John Hubbard
Cc: Danilo Krummrich, Alice Ryhl, David Airlie, Simona Vetter,
Alistair Popple, Joel Fernandes, Timur Tabi, Edwin Peer,
Eliot Courtney, nouveau, rust-for-linux, dri-devel, linux-kernel
On Mon Mar 9, 2026 at 11:06 AM JST, John Hubbard wrote:
> On 3/8/26 6:52 PM, Alexandre Courbot wrote:
>> On Fri Mar 6, 2026 at 1:52 PM JST, Alexandre Courbot wrote:
>>> gpu: nova-core: create falcon firmware DMA objects lazily
>> [acourbot@nvidia.com: add TODO item to switch back to a coherent
>> allocation when it becomes convenient to do so.]
>>> gpu: nova-core: falcon: add constant for memory block alignment
>>> gpu: nova-core: falcon: rename load parameters to reflect DMA dependency
>> [acourbot@nvidia.com: fixup order of import items.]
>>> gpu: nova-core: falcon: remove FalconFirmware's dependency on FalconDmaLoadable
>>> gpu: nova-core: move brom_params and boot_addr to FalconFirmware
>>> gpu: nova-core: falcon: remove unwarranted safety check in dma_load
>>> gpu: nova-core: make Chipset::arch() const
>>> gpu: nova-core: add gen_bootloader firmware to ModInfoBuilder
>>> gpu: nova-core: add PIO support for loading firmware images
>>> gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing
>>
>> All the above pushed to drm-rust-next, thanks!
>>
>
> Amazing! I'll start testing on Turing locally, in addition to Blackwell
> and Ampere, now. Exciting!
>
> Congratulations to Timur Tabi, and all of the expert reviewers and
> refactor-ers to!
Note that you still need to cherry-pick one of the two non-merged
patches for probe to complete properly:
https://lore.kernel.org/rust-for-linux/20260306-turing_prep-v11-9-8f0042c5d026@nvidia.com/
I should maybe have pushed the whole series, but would like to get at
least one Reviewed-by before I do so, for good conscience.
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-06 4:52 [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
` (12 preceding siblings ...)
2026-03-09 1:52 ` [PATCH v11 00/12] gpu: nova-core: add Turing support Alexandre Courbot
@ 2026-03-09 19:48 ` Ewan Chorynski
2026-03-09 20:04 ` John Hubbard
13 siblings, 1 reply; 31+ messages in thread
From: Ewan Chorynski @ 2026-03-09 19:48 UTC (permalink / raw)
To: Alexandre Courbot, Danilo Krummrich, Alice Ryhl, David Airlie,
Simona Vetter
Cc: John Hubbard, Alistair Popple, Joel Fernandes, Timur Tabi,
Edwin Peer, Eliot Courtney, nouveau, rust-for-linux, dri-devel,
linux-kernel
On Fri Mar 6, 2026 at 5:52 AM CET, Alexandre Courbot wrote:
> This patchset adds the remaining support required for booting the GSP on
> Turing.
>
> We did a deep dive with Eliot looking for the reasons why some fields
> involved in the bootloader are ignored or used apparently
> inconsistently, and this results in a more documented flow and a few
> fixes. Apart from that, this series seems to be stabilizing and
> successfully probes my TU106:
>
> NovaCore 0000:08:00.0: NVIDIA (Chipset: TU106, Architecture: Turing, Revision: a.1)
> NovaCore 0000:08:00.0: GPU name: NVIDIA GeForce RTX 2070
>
> This series is based on `drm-rust-next`. A tree with all the patches is
> available at [1].
>
> [1] https://github.com/Gnurou/linux/tree/b4/turing
>
> Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
>
> Changes in v11:
> - Fix build error/warnings and rustfmt formatting.
> - Address incorrect IMEM section start offsets in FalconUCodeDescV2
> and better document fields usage and unused fields.
> - Use `get`/`get_mut` instead of direct array indexing when accessing
> firmware content.
> - Link to v10: https://patch.msgid.link/20260301-turing_prep-v10-0-dde5ee437c60@nvidia.com
>
> Changes in v10:
> - Store the firmwares into a regular KVec and move them into a DMA
> object only when actually loading using DMA.
> - Use `try_update` when updating the `NV_PFALCON_FBIF_TRANSCFG` register
> array as its index is not build-time proven to be valid.
> - Fix alignment issue when processing imem section of the FWSEC
> bootloader (thanks Eliot!).
> - Link to v9: https://patch.msgid.link/20260212-turing_prep-v9-0-238520ad8799@nvidia.com
>
> Changes in v9:
> - Add a few preparatory patches to simplify the actual feature patches.
> - Use a wrapping type for the bootloader.
> - Simplify the falcon loading code and move the complexity to the
> firmware types.
> - Add the generic bootloader files to `ModInfoBuilder`.
> - Link to v8: https://lore.kernel.org/all/20260122222848.2555890-1-ttabi@nvidia.com/
>
> ---
> Alexandre Courbot (10):
> gpu: nova-core: create falcon firmware DMA objects lazily
> gpu: nova-core: falcon: add constant for memory block alignment
> gpu: nova-core: falcon: rename load parameters to reflect DMA dependency
> gpu: nova-core: falcon: remove FalconFirmware's dependency on FalconDmaLoadable
> gpu: nova-core: move brom_params and boot_addr to FalconFirmware
> gpu: nova-core: falcon: remove unwarranted safety check in dma_load
> gpu: nova-core: firmware: add comments to justify v3 header values
> gpu: nova-core: firmware: fix and explain v2 header offsets computations
> gpu: nova-core: make Chipset::arch() const
> gpu: nova-core: add gen_bootloader firmware to ModInfoBuilder
>
> Timur Tabi (2):
> gpu: nova-core: add PIO support for loading firmware images
> gpu: nova-core: use the Generic Bootloader to boot FWSEC on Turing
>
> drivers/gpu/nova-core/falcon.rs | 315 ++++++++++++++++---
> drivers/gpu/nova-core/falcon/hal.rs | 6 +-
> drivers/gpu/nova-core/firmware.rs | 107 ++++---
> drivers/gpu/nova-core/firmware/booter.rs | 65 ++--
> drivers/gpu/nova-core/firmware/fwsec.rs | 129 +++-----
> drivers/gpu/nova-core/firmware/fwsec/bootloader.rs | 348 +++++++++++++++++++++
> drivers/gpu/nova-core/gpu.rs | 9 +-
> drivers/gpu/nova-core/gsp/boot.rs | 17 +-
> drivers/gpu/nova-core/regs.rs | 30 ++
> 9 files changed, 820 insertions(+), 206 deletions(-)
> ---
> base-commit: 15da5bc9f3adab7242867db0251fe451ac3ddb72
> change-id: 20260204-turing_prep-6f6f54fe1850
>
> Best regards,
Hi,
I just want to remind that there is still issues for some Turing cards
with the firmware used by Nova (570.144) and this patchset still suffer
from the issue.
I am not able to probe on my GeForce GTX 1650 Mobile :
[ 2.246095] NovaCore 0000:01:00.0: NVIDIA (Chipset: TU117, Architecture: Turing, Revision: a.1)
[ 2.722681] NovaCore 0000:01:00.0: Booter-load failed with error 0x31
However nouveau does not probe either with this firmware so that's not
really this patchset fault.
Are there any plans to check this to enable support on all Turing cards ?
I already reported this error in the V4 patch [1] for context.
Feel free to ask me if you need additional tests or results.
[1]: https://lore.kernel.org/rust-for-linux/DFA1CUMND2ME.1D3PAJW641QHM@ik.me/T/#u
Regards,
Ewan
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 19:48 ` Ewan Chorynski
@ 2026-03-09 20:04 ` John Hubbard
2026-03-09 20:18 ` Timur Tabi
0 siblings, 1 reply; 31+ messages in thread
From: John Hubbard @ 2026-03-09 20:04 UTC (permalink / raw)
To: Ewan Chorynski, Alexandre Courbot, Danilo Krummrich, Alice Ryhl,
David Airlie, Simona Vetter
Cc: Alistair Popple, Joel Fernandes, Timur Tabi, Edwin Peer,
Eliot Courtney, nouveau, rust-for-linux, dri-devel, linux-kernel
On 3/9/26 12:48 PM, Ewan Chorynski wrote:
> On Fri Mar 6, 2026 at 5:52 AM CET, Alexandre Courbot wrote:
...
> I am not able to probe on my GeForce GTX 1650 Mobile :
>
> [ 2.246095] NovaCore 0000:01:00.0: NVIDIA (Chipset: TU117, Architecture: Turing, Revision: a.1)
> [ 2.722681] NovaCore 0000:01:00.0: Booter-load failed with error 0x31
I have that exact card available, so I'll give this a quick test and see
what's missing or wrong, now that Alex has pushed the entire Turing support
set up to drm-rust-next.
>
> However nouveau does not probe either with this firmware so that's not
> really this patchset fault.
>
> Are there any plans to check this to enable support on all Turing cards ?
Yes, the plan is that Nova will support all Turing and later GPUs.
thanks,
--
John Hubbard
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 20:04 ` John Hubbard
@ 2026-03-09 20:18 ` Timur Tabi
2026-03-09 20:29 ` John Hubbard
0 siblings, 1 reply; 31+ messages in thread
From: Timur Tabi @ 2026-03-09 20:18 UTC (permalink / raw)
To: ewan.chorynski@ik.me, Alexandre Courbot, dakr@kernel.org,
aliceryhl@google.com, airlied@gmail.com, John Hubbard,
simona@ffwll.ch
Cc: Alistair Popple, Edwin Peer, dri-devel@lists.freedesktop.org,
rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org,
nouveau@lists.freedesktop.org, Joel Fernandes, Eliot Courtney
On Mon, 2026-03-09 at 13:04 -0700, John Hubbard wrote:
>
> I have that exact card available, so I'll give this a quick test and see
> what's missing or wrong, now that Alex has pushed the entire Turing support
> set up to drm-rust-next.
The TU117 is technically a mobile chip, and its VBIOS is different. My initial version of the
Turing patches would "ignore" the problematic VBIOS sections, so perhaps this changed.
>
> >
> > However nouveau does not probe either with this firmware so that's not
> > really this patchset fault.
Now *that* is interesting. Nouveau does generally work on TU117s.
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 20:18 ` Timur Tabi
@ 2026-03-09 20:29 ` John Hubbard
2026-03-09 20:39 ` Timur Tabi
2026-03-09 21:00 ` Ewan Chorynski
0 siblings, 2 replies; 31+ messages in thread
From: John Hubbard @ 2026-03-09 20:29 UTC (permalink / raw)
To: Timur Tabi, ewan.chorynski@ik.me, Alexandre Courbot,
dakr@kernel.org, aliceryhl@google.com, airlied@gmail.com,
simona@ffwll.ch
Cc: Alistair Popple, Edwin Peer, dri-devel@lists.freedesktop.org,
rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org,
nouveau@lists.freedesktop.org, Joel Fernandes, Eliot Courtney
On 3/9/26 1:18 PM, Timur Tabi wrote:
> On Mon, 2026-03-09 at 13:04 -0700, John Hubbard wrote:
>>
>> I have that exact card available, so I'll give this a quick test and see
>> what's missing or wrong, now that Alex has pushed the entire Turing support
>> set up to drm-rust-next.
>
> The TU117 is technically a mobile chip, and its VBIOS is different. My initial version of the
> Turing patches would "ignore" the problematic VBIOS sections, so perhaps this changed.
>
No repro on the latest drm-rust-next branch:
NovaCore 0000:e1:00.0: Probe Nova Core GPU driver.
NovaCore 0000:e1:00.0: NVIDIA (Chipset: TU117, Architecture: Turing, Revision: a.1)
NovaCore 0000:e1:00.0: Found BIOS image: size: 0xe600, type: Ok(PciAt), last: false
NovaCore 0000:e1:00.0: Found BIOS image: size: 0x11000, type: Ok(Efi), last: false
NovaCore 0000:e1:00.0: Found BIOS image: size: 0xc200, type: Ok(FwSec), last: false
NovaCore 0000:e1:00.0: Found BIOS image: size: 0x22400, type: Ok(FwSec), last: false
NovaCore 0000:e1:00.0: Invalid signature for NpdeStruct: [1, 1, 66, 86]
NovaCore 0000:e1:00.0: Invalid signature for NpdeStruct: [1, 1, 66, 86]
NovaCore 0000:e1:00.0: Found BIOS image: size: 0x1a00, type: Ok(Nbsi), last: true
NovaCore 0000:e1:00.0: PmuLookupTableEntry desc: V2(
FalconUCodeDescV2 {
hdr: 3932673,
stored_size: 39968,
uncompressed_size: 39968,
virtual_entry: 0,
interface_offset: 224,
imem_phys_base: 0,
imem_load_size: 38912,
imem_virt_base: 0,
imem_sec_base: 1024,
imem_sec_size: 37888,
dmem_offset: 38912,
dmem_phys_base: 0,
dmem_load_size: 1056,
alt_imem_load_size: 38912,
alt_dmem_load_size: 26168,
},
)
NovaCore 0000:e1:00.0: FbLayout {
fb: 0x0..0x100000000,
vga_workspace: 0xfff00000..0x100000000,
frts: 0xffe00000..0xfff00000,
boot: 0xffdff000..0xffe00000,
elf: 0xfe2c0000..0xffdf4ea0,
wpr2_heap: 0xf7900000..0xfe200000,
wpr2: 0xf7800000..0xfff00000,
heap: 0xf7700000..0xf7800000,
vf_partition_count: 0x0,
}
NovaCore 0000:e1:00.0: WPR2: 0xffe00000-0xffee0000
NovaCore 0000:e1:00.0: GPU instance built
NovaCore 0000:e1:00.0: GSP RPC: send: seq# 0, function=GspSetSystemInfo, length=0x3f0
NovaCore 0000:e1:00.0: GSP RPC: send: seq# 1, function=SetRegistry, length=0xc5
NovaCore 0000:e1:00.0: GSP MBOX0: 0xffffe000, MBOX1: 0x0
NovaCore 0000:e1:00.0: Using SEC2 to load and run the booter_load firmware...
NovaCore 0000:e1:00.0: SEC2 MBOX0: 0x0, MBOX10x0
NovaCore 0000:e1:00.0: RISC-V active? true
NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GspRunCpuSequencer), length=0x820
NovaCore 0000:e1:00.0: Running CPU Sequencer commands
NovaCore 0000:e1:00.0: CPU Sequencer commands completed successfully
NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GspPostNoCat), length=0x50c
NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GspPostNoCat), length=0x50c
NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GspInitDone), length=0x50
NovaCore 0000:e1:00.0: GSP RPC: send: seq# 2, function=GetGspStaticInfo, length=0x6c8
NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GetGspStaticInfo), length=0x6c8
NovaCore 0000:e1:00.0: GPU name: NVIDIA GeForce GTX 1650
>>
>>>
>>> However nouveau does not probe either with this firmware so that's not
>>> really this patchset fault.
>
> Now *that* is interesting. Nouveau does generally work on TU117s.
>
thanks,
--
John Hubbard
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 20:29 ` John Hubbard
@ 2026-03-09 20:39 ` Timur Tabi
2026-03-09 21:00 ` Ewan Chorynski
1 sibling, 0 replies; 31+ messages in thread
From: Timur Tabi @ 2026-03-09 20:39 UTC (permalink / raw)
To: ewan.chorynski@ik.me, Alexandre Courbot, dakr@kernel.org,
aliceryhl@google.com, airlied@gmail.com, John Hubbard,
simona@ffwll.ch
Cc: Alistair Popple, Eliot Courtney, dri-devel@lists.freedesktop.org,
rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org,
nouveau@lists.freedesktop.org, Joel Fernandes, Edwin Peer
On Mon, 2026-03-09 at 13:29 -0700, John Hubbard wrote:
> On 3/9/26 1:18 PM, Timur Tabi wrote:
> > On Mon, 2026-03-09 at 13:04 -0700, John Hubbard wrote:
> > >
> > > I have that exact card available, so I'll give this a quick test and see
> > > what's missing or wrong, now that Alex has pushed the entire Turing support
> > > set up to drm-rust-next.
> >
> > The TU117 is technically a mobile chip, and its VBIOS is different. My initial version of the
> > Turing patches would "ignore" the problematic VBIOS sections, so perhaps this changed.
> >
>
> No repro on the latest drm-rust-next branch:
>
> NovaCore 0000:e1:00.0: Probe Nova Core GPU driver.
> NovaCore 0000:e1:00.0: NVIDIA (Chipset: TU117, Architecture: Turing, Revision: a.1)
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0xe600, type: Ok(PciAt), last: false
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0x11000, type: Ok(Efi), last: false
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0xc200, type: Ok(FwSec), last: false
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0x22400, type: Ok(FwSec), last: false
> NovaCore 0000:e1:00.0: Invalid signature for NpdeStruct: [1, 1, 66, 86]
> NovaCore 0000:e1:00.0: Invalid signature for NpdeStruct: [1, 1, 66, 86]
So this is the problematic section that gets ignored. It's on my TODO list to fix this, but last
time I looked at it, the documentation I had on the VBIOS layout did not align with the VBIOS on my
TU117.
> [ 2.246095] NovaCore 0000:01:00.0: NVIDIA (Chipset: TU117, Architecture: Turing, Revision: a.1)
> [ 2.722681] NovaCore 0000:01:00.0: Booter-load failed with error 0x31
>
> However nouveau does not probe either with this firmware so that's not
> really this patchset fault.
So Booter-load error 0x31 means that Booter technically did start, but it aborted very early.
Unfortunately, this is very difficult to debug in the field. Normally what I would do is build
custom versions of booter-load to see where it fails. I cannot do this without the card in my hand.
The first thing I would do is verify that GspFwWprMeta does not have nonsensical values.
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 20:29 ` John Hubbard
2026-03-09 20:39 ` Timur Tabi
@ 2026-03-09 21:00 ` Ewan Chorynski
2026-03-09 21:05 ` Timur Tabi
1 sibling, 1 reply; 31+ messages in thread
From: Ewan Chorynski @ 2026-03-09 21:00 UTC (permalink / raw)
To: John Hubbard, Timur Tabi, ewan.chorynski@ik.me, Alexandre Courbot,
dakr@kernel.org, aliceryhl@google.com, airlied@gmail.com,
simona@ffwll.ch
Cc: Alistair Popple, Edwin Peer, dri-devel@lists.freedesktop.org,
rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org,
nouveau@lists.freedesktop.org, Joel Fernandes, Eliot Courtney
On Mon Mar 9, 2026 at 9:29 PM CET, John Hubbard wrote:
> On 3/9/26 1:18 PM, Timur Tabi wrote:
>> On Mon, 2026-03-09 at 13:04 -0700, John Hubbard wrote:
>>>
>>> I have that exact card available, so I'll give this a quick test and see
>>> what's missing or wrong, now that Alex has pushed the entire Turing support
>>> set up to drm-rust-next.
>>
>> The TU117 is technically a mobile chip, and its VBIOS is different. My initial version of the
>> Turing patches would "ignore" the problematic VBIOS sections, so perhaps this changed.
>>
>
> No repro on the latest drm-rust-next branch:
I guess I may have an issue with my linux-firmware. I have no stable
right now so I can't download the latest one but I'll try
soon. On which commit on linux-firmware are you ?
>
> NovaCore 0000:e1:00.0: Probe Nova Core GPU driver.
> NovaCore 0000:e1:00.0: NVIDIA (Chipset: TU117, Architecture: Turing, Revision: a.1)
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0xe600, type: Ok(PciAt), last: false
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0x11000, type: Ok(Efi), last: false
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0xc200, type: Ok(FwSec), last: false
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0x22400, type: Ok(FwSec), last: false
> NovaCore 0000:e1:00.0: Invalid signature for NpdeStruct: [1, 1, 66, 86]
> NovaCore 0000:e1:00.0: Invalid signature for NpdeStruct: [1, 1, 66, 86]
> NovaCore 0000:e1:00.0: Found BIOS image: size: 0x1a00, type: Ok(Nbsi), last: true
> NovaCore 0000:e1:00.0: PmuLookupTableEntry desc: V2(
> FalconUCodeDescV2 {
> hdr: 3932673,
> stored_size: 39968,
> uncompressed_size: 39968,
> virtual_entry: 0,
> interface_offset: 224,
> imem_phys_base: 0,
> imem_load_size: 38912,
> imem_virt_base: 0,
> imem_sec_base: 1024,
> imem_sec_size: 37888,
> dmem_offset: 38912,
> dmem_phys_base: 0,
> dmem_load_size: 1056,
> alt_imem_load_size: 38912,
> alt_dmem_load_size: 26168,
> },
> )
> NovaCore 0000:e1:00.0: FbLayout {
> fb: 0x0..0x100000000,
> vga_workspace: 0xfff00000..0x100000000,
> frts: 0xffe00000..0xfff00000,
> boot: 0xffdff000..0xffe00000,
> elf: 0xfe2c0000..0xffdf4ea0,
> wpr2_heap: 0xf7900000..0xfe200000,
> wpr2: 0xf7800000..0xfff00000,
> heap: 0xf7700000..0xf7800000,
> vf_partition_count: 0x0,
> }
> NovaCore 0000:e1:00.0: WPR2: 0xffe00000-0xffee0000
> NovaCore 0000:e1:00.0: GPU instance built
> NovaCore 0000:e1:00.0: GSP RPC: send: seq# 0, function=GspSetSystemInfo, length=0x3f0
> NovaCore 0000:e1:00.0: GSP RPC: send: seq# 1, function=SetRegistry, length=0xc5
> NovaCore 0000:e1:00.0: GSP MBOX0: 0xffffe000, MBOX1: 0x0
> NovaCore 0000:e1:00.0: Using SEC2 to load and run the booter_load firmware...
> NovaCore 0000:e1:00.0: SEC2 MBOX0: 0x0, MBOX10x0
> NovaCore 0000:e1:00.0: RISC-V active? true
> NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GspRunCpuSequencer), length=0x820
> NovaCore 0000:e1:00.0: Running CPU Sequencer commands
> NovaCore 0000:e1:00.0: CPU Sequencer commands completed successfully
> NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GspPostNoCat), length=0x50c
> NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GspPostNoCat), length=0x50c
> NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GspInitDone), length=0x50
> NovaCore 0000:e1:00.0: GSP RPC: send: seq# 2, function=GetGspStaticInfo, length=0x6c8
> NovaCore 0000:e1:00.0: GSP RPC: receive: seq# 0, function=Ok(GetGspStaticInfo), length=0x6c8
> NovaCore 0000:e1:00.0: GPU name: NVIDIA GeForce GTX 1650
>
>
>>>
>>>>
>>>> However nouveau does not probe either with this firmware so that's not
>>>> really this patchset fault.
>>
>> Now *that* is interesting. Nouveau does generally work on TU117s.
>>
>
> thanks,
^ permalink raw reply [flat|nested] 31+ messages in thread* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 21:00 ` Ewan Chorynski
@ 2026-03-09 21:05 ` Timur Tabi
2026-03-09 21:16 ` Ewan Chorynski
0 siblings, 1 reply; 31+ messages in thread
From: Timur Tabi @ 2026-03-09 21:05 UTC (permalink / raw)
To: ewan.chorynski@ik.me, Alexandre Courbot, dakr@kernel.org,
aliceryhl@google.com, airlied@gmail.com, John Hubbard,
simona@ffwll.ch
Cc: Alistair Popple, Eliot Courtney, dri-devel@lists.freedesktop.org,
rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org,
nouveau@lists.freedesktop.org, Joel Fernandes, Edwin Peer
On Mon, 2026-03-09 at 22:00 +0100, Ewan Chorynski wrote:
> On Mon Mar 9, 2026 at 9:29 PM CET, John Hubbard wrote:
> > On 3/9/26 1:18 PM, Timur Tabi wrote:
> > > On Mon, 2026-03-09 at 13:04 -0700, John Hubbard wrote:
> > > >
> > > > I have that exact card available, so I'll give this a quick test and see
> > > > what's missing or wrong, now that Alex has pushed the entire Turing support
> > > > set up to drm-rust-next.
> > >
> > > The TU117 is technically a mobile chip, and its VBIOS is different. My initial version of the
> > > Turing patches would "ignore" the problematic VBIOS sections, so perhaps this changed.
> > >
> >
> > No repro on the latest drm-rust-next branch:
>
> I guess I may have an issue with my linux-firmware. I have no stable
> right now so I can't download the latest one but I'll try
> soon. On which commit on linux-firmware are you ?
There's only one version of linux-firmware that works with Nova, and you didn't have it, it wouldn't
boot at all.
Although, now that I think about it, I'm assuming that on Turing, if gen_bootloader is absent,
NovaCore will not even try to boot. That file was added recently and is missing in most distros
today.
/lib/firmware/nvidia/tu102/gsp/gen_bootloader-570.144.bin (or its zstd compressed version)
If you have this file, then you have everything you need to boot NovaCore on Turing.
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 21:05 ` Timur Tabi
@ 2026-03-09 21:16 ` Ewan Chorynski
2026-03-09 21:22 ` Timur Tabi
0 siblings, 1 reply; 31+ messages in thread
From: Ewan Chorynski @ 2026-03-09 21:16 UTC (permalink / raw)
To: Timur Tabi, ewan.chorynski@ik.me, Alexandre Courbot,
dakr@kernel.org, aliceryhl@google.com, airlied@gmail.com,
John Hubbard, simona@ffwll.ch
Cc: Alistair Popple, Eliot Courtney, dri-devel@lists.freedesktop.org,
rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org,
nouveau@lists.freedesktop.org, Joel Fernandes, Edwin Peer
On Mon Mar 9, 2026 at 10:05 PM CET, Timur Tabi wrote:
> On Mon, 2026-03-09 at 22:00 +0100, Ewan Chorynski wrote:
>> On Mon Mar 9, 2026 at 9:29 PM CET, John Hubbard wrote:
>> > On 3/9/26 1:18 PM, Timur Tabi wrote:
>> > > On Mon, 2026-03-09 at 13:04 -0700, John Hubbard wrote:
>> > > >
>> > > > I have that exact card available, so I'll give this a quick test and see
>> > > > what's missing or wrong, now that Alex has pushed the entire Turing support
>> > > > set up to drm-rust-next.
>> > >
>> > > The TU117 is technically a mobile chip, and its VBIOS is different. My initial version of the
>> > > Turing patches would "ignore" the problematic VBIOS sections, so perhaps this changed.
>> > >
>> >
>> > No repro on the latest drm-rust-next branch:
>>
>> I guess I may have an issue with my linux-firmware. I have no stable
>> right now so I can't download the latest one but I'll try
>> soon. On which commit on linux-firmware are you ?
>
> There's only one version of linux-firmware that works with Nova, and you didn't have it, it wouldn't
> boot at all.
>
> Although, now that I think about it, I'm assuming that on Turing, if gen_bootloader is absent,
> NovaCore will not even try to boot. That file was added recently and is missing in most distros
> today.
>
> /lib/firmware/nvidia/tu102/gsp/gen_bootloader-570.144.bin (or its zstd compressed version)
>
> If you have this file, then you have everything you need to boot NovaCore on Turing.
I had this file installed but I think I broke something when I updated.
I tried to redo my installation from the tarball I had and now it is
probing, so the issue was indeed on my side with my firmware.
Thanks for trying the repro and sorry for the false alarm.
Have a good day
Ewan
^ permalink raw reply [flat|nested] 31+ messages in thread
* Re: [PATCH v11 00/12] gpu: nova-core: add Turing support
2026-03-09 21:16 ` Ewan Chorynski
@ 2026-03-09 21:22 ` Timur Tabi
0 siblings, 0 replies; 31+ messages in thread
From: Timur Tabi @ 2026-03-09 21:22 UTC (permalink / raw)
To: ewan.chorynski@ik.me, Alexandre Courbot, dakr@kernel.org,
aliceryhl@google.com, airlied@gmail.com, John Hubbard,
simona@ffwll.ch
Cc: Alistair Popple, Edwin Peer, dri-devel@lists.freedesktop.org,
rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org,
nouveau@lists.freedesktop.org, Joel Fernandes, Eliot Courtney
On Mon, 2026-03-09 at 22:16 +0100, Ewan Chorynski wrote:
> I had this file installed but I think I broke something when I updated.
> I tried to redo my installation from the tarball I had and now it is
> probing, so the issue was indeed on my side with my firmware.
>
> Thanks for trying the repro and sorry for the false alarm.
It would be good to know exactly how your broken /lib/firmware caused booter-load to fail.
^ permalink raw reply [flat|nested] 31+ messages in thread