Re: [PATCH v7 18/31] gpu: nova-core: add MCTP/NVDM protocol types for firmware communication

["Alexandre Courbot" <acourbot@nvidia.com>]

On Wed Mar 18, 2026 at 9:21 AM JST, Danilo Krummrich wrote:
> On Wed Mar 18, 2026 at 1:01 AM CET, John Hubbard wrote:
>> On 3/17/26 3:53 PM, John Hubbard wrote:
>> ...
>>> +bitfield! {
>>> +    pub(crate) struct MctpHeader(u32), "MCTP transport header for NVIDIA firmware messages." {
>>> +        31:31 som as bool, "Start-of-message bit.";
>>> +        30:30 eom as bool, "End-of-message bit.";
>>> +        29:28 seq as u8, "Packet sequence number.";
>>> +        23:16 seid as u8, "Source endpoint ID.";
>>
>> hmmm, I seem to remember my very slightly younger self insisting
>> that fields be listed from lowest to highest bits. And now I've
>> violated that in both headers in this patch. arghh
>
> My now slightly older self still thinks that what you have above is actually the
> way to go. So, I think your current self intuitively did the right thing. :P
>
> It should be either
>
> 	31:16
> 	15:0
>
> or it should be
>
> 	0:15
> 	16:31
>
> with a strong preference for the former, but this
>
> 	15:0
> 	31:16
>
> still looks pretty odd to me.

Mmm, that's the order `regs.rs` currently uses. I don't have any
particular problem with it tbh.

The second form (`0:15`) is going to be rejected by the macro - it
expects the high bit first.