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charset=UTF-8 Date: Mon, 23 Mar 2026 22:02:47 +0900 Message-Id: Cc: "Danilo Krummrich" , "Joel Fernandes" , "Timur Tabi" , "Alistair Popple" , "Eliot Courtney" , "Shashank Sharma" , "Zhi Wang" , "David Airlie" , "Simona Vetter" , "Bjorn Helgaas" , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , , "LKML" Subject: Re: [PATCH v7 05/31] gpu: nova-core: set DMA mask width based on GPU architecture From: "Alexandre Courbot" To: "John Hubbard" References: <20260317225355.549853-1-jhubbard@nvidia.com> <20260317225355.549853-6-jhubbard@nvidia.com> In-Reply-To: <20260317225355.549853-6-jhubbard@nvidia.com> X-ClientProxiedBy: TY4PR01CA0126.jpnprd01.prod.outlook.com (2603:1096:405:379::9) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|CH3PR12MB8850:EE_ X-MS-Office365-Filtering-Correlation-Id: 085e2116-7465-4d25-75e5-08de88dc7d16 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|7416014|1800799024|366016|10070799003|7053199007|22082099003|56012099003|18002099003; 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Move Spec creation into probe() so the > architecture is known before setting the DMA mask, and pass the Spec > into Gpu::new(). > > Cc: Danilo Krummrich > Cc: Gary Guo Why the Ccs? Some patches in the series seem to have random people Cc'd to them. > Signed-off-by: John Hubbard > --- > drivers/gpu/nova-core/driver.rs | 28 +++++++-------- > drivers/gpu/nova-core/gpu.rs | 60 +++++++++++++++++++-------------- > 2 files changed, 47 insertions(+), 41 deletions(-) > > diff --git a/drivers/gpu/nova-core/driver.rs b/drivers/gpu/nova-core/driv= er.rs > index 84b0e1703150..41227d29934e 100644 > --- a/drivers/gpu/nova-core/driver.rs > +++ b/drivers/gpu/nova-core/driver.rs > @@ -5,7 +5,6 @@ > device::Core, > devres::Devres, > dma::Device, > - dma::DmaMask, > pci, > pci::{ > Class, > @@ -23,7 +22,10 @@ > }, > }; > =20 > -use crate::gpu::Gpu; > +use crate::gpu::{ > + Gpu, > + Spec, // > +}; > =20 > /// Counter for generating unique auxiliary device IDs. > static AUXILIARY_ID_COUNTER: Atomic =3D Atomic::new(0); > @@ -38,14 +40,6 @@ pub(crate) struct NovaCore { > =20 > const BAR0_SIZE: usize =3D SZ_16M; > =20 > -// For now we only support Ampere which can use up to 47-bit DMA address= es. > -// > -// TODO: Add an abstraction for this to support newer GPUs which may sup= port > -// larger DMA addresses. Limiting these GPUs to smaller address widths w= on't > -// have any adverse affects, unless installed on systems which require l= arger > -// DMA addresses. These systems should be quite rare. > -const GPU_DMA_BITS: u32 =3D 47; > - > pub(crate) type Bar0 =3D pci::Bar; > =20 > kernel::pci_device_table!( > @@ -84,18 +78,20 @@ fn probe(pdev: &pci::Device, _info: &Self::IdIn= fo) -> impl PinInit pdev.enable_device_mem()?; > pdev.set_master(); > =20 > - // SAFETY: No concurrent DMA allocations or mappings can be = made because > - // the device is still being probed and therefore isn't bein= g used by > - // other threads of execution. > - unsafe { pdev.dma_set_mask_and_coherent(DmaMask::new::())? }; > - > let bar =3D Arc::pin_init( > pdev.iomap_region_sized::(0, c"nova-core/bar0= "), > GFP_KERNEL, > )?; > + let spec =3D Spec::new(pdev.as_ref(), bar.access(pdev.as_ref= ())?)?; > + dev_info!(pdev, "NVIDIA ({})\n", spec); > + > + // SAFETY: No concurrent DMA allocations or mappings can be = made because > + // the device is still being probed and therefore isn't bein= g used by > + // other threads of execution. > + unsafe { pdev.dma_set_mask_and_coherent(spec.chipset().arch(= ).dma_mask())? }; > =20 > Ok(try_pin_init!(Self { > - gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_re= f())?), > + gpu <- Gpu::new(pdev, bar.clone(), bar.access(pdev.as_re= f())?, spec), > _reg <- auxiliary::Registration::new( > pdev.as_ref(), > c"nova-drm", > diff --git a/drivers/gpu/nova-core/gpu.rs b/drivers/gpu/nova-core/gpu.rs > index 8f317d213908..9e140463603b 100644 > --- a/drivers/gpu/nova-core/gpu.rs > +++ b/drivers/gpu/nova-core/gpu.rs > @@ -3,6 +3,7 @@ > use kernel::{ > device, > devres::Devres, > + dma::DmaMask, > fmt, > pci, > prelude::*, > @@ -162,6 +163,19 @@ pub(crate) enum Architecture { > Blackwell =3D 0x1b, > } > =20 > +impl Architecture { > + /// Returns the DMA mask supported by this architecture. > + /// > + /// Hopper and Blackwell support 52-bit DMA addresses, while earlier > + /// architectures (Turing, Ampere, Ada) support 47-bit. This last sentence is unneeded, we describe what methods provide in doccomments, not how they do it or what the result will be. > + pub(crate) const fn dma_mask(&self) -> DmaMask { > + match self { > + Self::Turing | Self::Ampere | Self::Ada =3D> DmaMask::new::<= 47>(), > + Self::Hopper | Self::Blackwell =3D> DmaMask::new::<52>(), > + } > + } > +} I see you introduce a `Gpu` HAL in the next patch. I think this should also be part of the HAL - there is no benefit in having this method const since the architecture is probed at runtime anyway. > + > impl TryFrom for Architecture { > type Error =3D Error; > =20 > @@ -211,7 +225,7 @@ pub(crate) struct Spec { > } > =20 > impl Spec { > - fn new(dev: &device::Device, bar: &Bar0) -> Result { > + pub(crate) fn new(dev: &device::Device, bar: &Bar0) -> Result = { > // Some brief notes about boot0 and boot42, in chronological ord= er: > // > // NV04 through NV50: > @@ -292,38 +306,34 @@ pub(crate) fn new<'a>( > pdev: &'a pci::Device, > devres_bar: Arc>, > bar: &'a Bar0, > + spec: Spec, > ) -> impl PinInit + 'a { > - pin_init::pin_init_scope(move || { > - let spec =3D Spec::new(pdev.as_ref(), bar)?; > - dev_info!(pdev, "NVIDIA ({})\n", spec); > - > - let chipset =3D spec.chipset(); > + let chipset =3D spec.chipset(); > =20 > - Ok(try_pin_init!(Self { > - // We must wait for GFW_BOOT completion before doing any= significant setup > - // on the GPU. > - _: { > - gfw::wait_gfw_boot_completion(bar) > - .inspect_err(|_| dev_err!(pdev, "GFW boot did no= t complete\n"))?; > - }, > + try_pin_init!(Self { What, and now we undo what we just did in patch 4? 0_o; What was that all for? I did a `git diff` between this step in the series and the state two steps above, and it seems to confirm my intuition on patch 4: you just need a few more `Copy` implementations. They can be added in this patch, and patch 4 dropped altogether.