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> =20 > pub(crate) type IoMem =3D kernel::io::mem::IoMem; > @@ -78,11 +84,15 @@ unsafe impl Send for TyrDrmDeviceData {} > unsafe impl Sync for TyrDrmDeviceData {} > =20 > fn issue_soft_reset(dev: &Device, iomem: &Devres) -> Resul= t { > - regs::GPU_CMD.write(dev, iomem, regs::GPU_CMD_SOFT_RESET)?; > + let io =3D (*iomem).access(dev)?; > + io.write_reg(GPU_COMMAND::reset(ResetMode::SoftReset)); > =20 > poll::read_poll_timeout( > - || regs::GPU_IRQ_RAWSTAT.read(dev, iomem), > - |status| *status & regs::GPU_IRQ_RAWSTAT_RESET_COMPLETED !=3D 0, > + || { > + let io =3D (*iomem).access(dev)?; > + Ok(io.read(GPU_IRQ_RAWSTAT)) > + }, > + |status| status.reset_completed(), > time::Delta::from_millis(1), > time::Delta::from_millis(100), > ) > @@ -127,7 +137,7 @@ fn probe( > gpu::l2_power_on(pdev.as_ref(), &iomem)?; > =20 > let gpu_info =3D GpuInfo::new(pdev.as_ref(), &iomem)?; > - gpu_info.log(pdev); > + gpu_info_log(pdev.as_ref(), &iomem)?; This causes all registers to be re-read again for some reason? Why is the function signature of `gpu_info_log` changing from a method to a standalone function? The commit message doesn't mention any. > =20 > let platform: ARef =3D pdev.into(); > =20 > diff --git a/drivers/gpu/drm/tyr/gpu.rs b/drivers/gpu/drm/tyr/gpu.rs > index a88775160f981e899e9c9b58debbda33e1b7244d..8ae39137a1d190ef026351d47= a6cdd89063ed0fb 100644 > --- a/drivers/gpu/drm/tyr/gpu.rs > +++ b/drivers/gpu/drm/tyr/gpu.rs > @@ -5,14 +5,16 @@ > DerefMut, // > }; > use kernel::{ > - bits::genmask_u32, > device::{ > Bound, > Device, // > }, > devres::Devres, > - io::poll, > - platform, > + io::{ > + poll, > + register::Array, > + Io, // > + }, > prelude::*, > time::Delta, > transmute::AsBytes, > @@ -21,7 +23,10 @@ > =20 > use crate::{ > driver::IoMem, > - regs, // > + regs::{ > + gpu_control::*, > + join_u64, // > + }, // > }; > =20 > /// Struct containing information that can be queried by userspace. This= is read from > @@ -29,120 +34,55 @@ > /// > /// # Invariants > /// > -/// - The layout of this struct identical to the C `struct drm_panthor_g= pu_info`. > +/// - The layout of this struct is identical to the C `struct drm_pantho= r_gpu_info`. > #[repr(transparent)] > #[derive(Clone, Copy)] > pub(crate) struct GpuInfo(pub(crate) uapi::drm_panthor_gpu_info); > =20 > impl GpuInfo { > pub(crate) fn new(dev: &Device, iomem: &Devres) -> Res= ult { > - let gpu_id =3D regs::GPU_ID.read(dev, iomem)?; > - let csf_id =3D regs::GPU_CSF_ID.read(dev, iomem)?; > - let gpu_rev =3D regs::GPU_REVID.read(dev, iomem)?; > - let core_features =3D regs::GPU_CORE_FEATURES.read(dev, iomem)?; > - let l2_features =3D regs::GPU_L2_FEATURES.read(dev, iomem)?; > - let tiler_features =3D regs::GPU_TILER_FEATURES.read(dev, iomem)= ?; > - let mem_features =3D regs::GPU_MEM_FEATURES.read(dev, iomem)?; > - let mmu_features =3D regs::GPU_MMU_FEATURES.read(dev, iomem)?; > - let thread_features =3D regs::GPU_THREAD_FEATURES.read(dev, iome= m)?; > - let max_threads =3D regs::GPU_THREAD_MAX_THREADS.read(dev, iomem= )?; > - let thread_max_workgroup_size =3D regs::GPU_THREAD_MAX_WORKGROUP= _SIZE.read(dev, iomem)?; > - let thread_max_barrier_size =3D regs::GPU_THREAD_MAX_BARRIER_SIZ= E.read(dev, iomem)?; > - let coherency_features =3D regs::GPU_COHERENCY_FEATURES.read(dev= , iomem)?; > - > - let texture_features =3D regs::GPU_TEXTURE_FEATURES0.read(dev, i= omem)?; > - > - let as_present =3D regs::GPU_AS_PRESENT.read(dev, iomem)?; > - > - let shader_present =3D u64::from(regs::GPU_SHADER_PRESENT_LO.rea= d(dev, iomem)?); > - let shader_present =3D > - shader_present | u64::from(regs::GPU_SHADER_PRESENT_HI.read(= dev, iomem)?) << 32; > - > - let tiler_present =3D u64::from(regs::GPU_TILER_PRESENT_LO.read(= dev, iomem)?); > - let tiler_present =3D > - tiler_present | u64::from(regs::GPU_TILER_PRESENT_HI.read(de= v, iomem)?) << 32; > - > - let l2_present =3D u64::from(regs::GPU_L2_PRESENT_LO.read(dev, i= omem)?); > - let l2_present =3D l2_present | u64::from(regs::GPU_L2_PRESENT_H= I.read(dev, iomem)?) << 32; > + let io =3D (*iomem).access(dev)?; > =20 > Ok(Self(uapi::drm_panthor_gpu_info { > - gpu_id, > - gpu_rev, > - csf_id, > - l2_features, > - tiler_features, > - mem_features, > - mmu_features, > - thread_features, > - max_threads, > - thread_max_workgroup_size, > - thread_max_barrier_size, > - coherency_features, > - // TODO: Add texture_features_{1,2,3}. > - texture_features: [texture_features, 0, 0, 0], > - as_present, > + gpu_id: io.read(GPU_ID).into_raw(), > + gpu_rev: io.read(REVIDR).into_raw(), > + csf_id: io.read(CSF_ID).into_raw(), > + l2_features: io.read(L2_FEATURES).into_raw(), > + tiler_features: io.read(TILER_FEATURES).into_raw(), > + mem_features: io.read(MEM_FEATURES).into_raw(), > + mmu_features: io.read(MMU_FEATURES).into_raw(), > + thread_features: io.read(THREAD_FEATURES).into_raw(), > + max_threads: io.read(THREAD_MAX_THREADS).into_raw(), > + thread_max_workgroup_size: io.read(THREAD_MAX_WORKGROUP_SIZE= ).into_raw(), > + thread_max_barrier_size: io.read(THREAD_MAX_BARRIER_SIZE).in= to_raw(), > + coherency_features: io.read(COHERENCY_FEATURES).into_raw(), > + texture_features: [ > + io.read(TEXTURE_FEATURES::at(0)).supported_formats().get= (), > + io.read(TEXTURE_FEATURES::at(1)).supported_formats().get= (), > + io.read(TEXTURE_FEATURES::at(2)).supported_formats().get= (), > + io.read(TEXTURE_FEATURES::at(3)).supported_formats().get= (), > + ], > + as_present: io.read(AS_PRESENT).into_raw(), > selected_coherency: uapi::drm_panthor_gpu_coherency_DRM_PANT= HOR_GPU_COHERENCY_NONE, > - shader_present, > - l2_present, > - tiler_present, > - core_features, > + shader_present: join_u64( > + io.read(SHADER_PRESENT_LO).into_raw(), > + io.read(SHADER_PRESENT_HI).into_raw(), > + ), > + l2_present: join_u64( > + io.read(L2_PRESENT_LO).into_raw(), > + io.read(L2_PRESENT_HI).into_raw(), > + ), > + tiler_present: join_u64( > + io.read(TILER_PRESENT_LO).into_raw(), > + io.read(TILER_PRESENT_HI).into_raw(), > + ), > + core_features: io.read(CORE_FEATURES).into_raw(), > + // Padding must be zero. > pad: 0, > + //GPU_FEATURES register is not available; it was introduced = in arch 11.x. > gpu_features: 0, > })) > } > - > - pub(crate) fn log(&self, pdev: &platform::Device) { > - let gpu_id =3D GpuId::from(self.gpu_id); > - > - let model_name =3D if let Some(model) =3D GPU_MODELS > - .iter() > - .find(|&f| f.arch_major =3D=3D gpu_id.arch_major && f.prod_m= ajor =3D=3D gpu_id.prod_major) > - { > - model.name > - } else { > - "unknown" > - }; > - > - dev_info!( > - pdev, > - "mali-{} id 0x{:x} major 0x{:x} minor 0x{:x} status 0x{:x}", > - model_name, > - self.gpu_id >> 16, > - gpu_id.ver_major, > - gpu_id.ver_minor, > - gpu_id.ver_status > - ); > - > - dev_info!( > - pdev, > - "Features: L2:{:#x} Tiler:{:#x} Mem:{:#x} MMU:{:#x} AS:{:#x}= ", > - self.l2_features, > - self.tiler_features, > - self.mem_features, > - self.mmu_features, > - self.as_present > - ); > - > - dev_info!( > - pdev, > - "shader_present=3D0x{:016x} l2_present=3D0x{:016x} tiler_pre= sent=3D0x{:016x}", > - self.shader_present, > - self.l2_present, > - self.tiler_present > - ); > - } > - > - /// Returns the number of virtual address bits supported by the GPU. > - #[expect(dead_code)] > - pub(crate) fn va_bits(&self) -> u32 { > - self.mmu_features & genmask_u32(0..=3D7) > - } > - > - /// Returns the number of physical address bits supported by the GPU= . > - #[expect(dead_code)] > - pub(crate) fn pa_bits(&self) -> u32 { > - (self.mmu_features >> 8) & genmask_u32(0..=3D7) > - } > } > =20 > impl Deref for GpuInfo { > @@ -182,38 +122,68 @@ struct GpuModels { > prod_major: 7, > }]; > =20 > -#[allow(dead_code)] > -pub(crate) struct GpuId { > - pub(crate) arch_major: u32, > - pub(crate) arch_minor: u32, > - pub(crate) arch_rev: u32, > - pub(crate) prod_major: u32, > - pub(crate) ver_major: u32, > - pub(crate) ver_minor: u32, > - pub(crate) ver_status: u32, > -} > - > -impl From for GpuId { > - fn from(value: u32) -> Self { > - GpuId { > - arch_major: (value & genmask_u32(28..=3D31)) >> 28, > - arch_minor: (value & genmask_u32(24..=3D27)) >> 24, > - arch_rev: (value & genmask_u32(20..=3D23)) >> 20, > - prod_major: (value & genmask_u32(16..=3D19)) >> 16, > - ver_major: (value & genmask_u32(12..=3D15)) >> 12, > - ver_minor: (value & genmask_u32(4..=3D11)) >> 4, > - ver_status: value & genmask_u32(0..=3D3), > - } > - } > +pub(crate) fn gpu_info_log(dev: &Device, iomem: &Devres) -= > Result { > + let io =3D (*iomem).access(dev)?; > + let gpu_id =3D io.read(GPU_ID); > + > + let model_name =3D if let Some(model) =3D GPU_MODELS.iter().find(|&f= | { > + f.arch_major =3D=3D gpu_id.arch_major().get() && f.prod_major = =3D=3D gpu_id.prod_major().get() > + }) { > + model.name > + } else { > + "unknown" > + }; > + > + dev_info!( > + dev, > + "mali-{} id 0x{:x} major 0x{:x} minor 0x{:x} status 0x{:x}", > + model_name, > + gpu_id.into_raw() >> 16, > + gpu_id.ver_major().get(), > + gpu_id.ver_minor().get(), > + gpu_id.ver_status().get() > + ); > + > + dev_info!( > + dev, > + "Features: L2:{:#x} Tiler:{:#x} Mem:{:#x} MMU:{:#x} AS:{:#x}", > + io.read(L2_FEATURES).into_raw(), > + io.read(TILER_FEATURES).into_raw(), > + io.read(MEM_FEATURES).into_raw(), > + io.read(MMU_FEATURES).into_raw(), > + io.read(AS_PRESENT).into_raw(), > + ); Without the signature change the old code is all accessing from self. Best, Gary > + > + dev_info!( > + dev, > + "shader_present=3D0x{:016x} l2_present=3D0x{:016x} tiler_present= =3D0x{:016x}", > + join_u64( > + io.read(SHADER_PRESENT_LO).into_raw(), > + io.read(SHADER_PRESENT_HI).into_raw(), > + ), > + join_u64( > + io.read(L2_PRESENT_LO).into_raw(), > + io.read(L2_PRESENT_HI).into_raw(), > + ), > + join_u64( > + io.read(TILER_PRESENT_LO).into_raw(), > + io.read(TILER_PRESENT_HI).into_raw(), > + ), > + ); > + Ok(()) > } > =20 > [snip]