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When present, the PROM shadow > method must parse this header to determine the offset where the PCI ROM > images actually begin, and adjust all subsequent reads accordingly. > > On most GPUs this is not needed because the IFR microcode has already > applied the ROM offset so that PROM reads transparently skip the header. > On GA100, for whatever reason, the IFR offset is not applied to PROM > reads. Therefore, the search for the PCI expansion must skip the IFR > header, if found. > > Signed-off-by: Timur Tabi > --- > drivers/gpu/nova-core/vbios.rs | 67 +++++++++++++++++++++++++++++++++- > 1 file changed, 66 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/nova-core/vbios.rs b/drivers/gpu/nova-core/vbios= .rs > index e726594eb130..000e823b9e47 100644 > --- a/drivers/gpu/nova-core/vbios.rs > +++ b/drivers/gpu/nova-core/vbios.rs > @@ -89,13 +89,78 @@ struct VbiosIterator<'a> { > last_found: bool, > } > =20 > +/// Offset of FIXED0 field in IFR header > +const NV_PBUS_IFR_FMT_FIXED0: usize =3D 0x00000000; > +/// Offset of FIXED1 field in IFR header > +const NV_PBUS_IFR_FMT_FIXED1: usize =3D 0x00000004; > +/// Offset of FIXED2 field in IFR header > +const NV_PBUS_IFR_FMT_FIXED2: usize =3D 0x00000008; > +/// IFR signature: ASCII "NVGI" as a little-endian u32. > +const NV_PBUS_IFR_FMT_FIXED0_SIGNATURE_VALUE: u32 =3D 0x4947564E; > +/// ROM directory signature: ASCII "RFRD" as a little-endian u32. > +const NV_ROM_DIRECTORY_IDENTIFIER: u32 =3D 0x44524652; > +/// Offset of the NV_PMGR_ROM_ADDR_OFFSET register in IFR Extended secti= on > +const IFR_SW_EXT_ROM_ADDR_OFFSET: usize =3D 4; > +/// Size of Redundant Firmware Flash Status section > +const RFW_FLASH_STATUS_SIZE: usize =3D 4096; > + > +bitfield! { > + struct IfrFixed1(u32) { > + 15:8 version as u8; > + 30:16 fixed_data_size as u16; > + } > +} > + > +bitfield! { > + struct IfrFixed2(u32) { > + 19:0 total_data_size as u32; > + } > +} Shouldn't this be using the `register!` macro instead? Best, Gary > + > impl<'a> VbiosIterator<'a> { > fn new(dev: &'a device::Device, bar0: &'a Bar0) -> Result { > + let signature =3D bar0.try_read32(ROM_OFFSET + NV_PBUS_IFR_FMT_F= IXED0)?; > + > + // The ROM may start with an Init-from-ROM (IFR) header before t= he PCI > + // Expansion ROM images. Most GPUs apply the IFR offset transpar= ently, but > + // GA100 does not, so we must skip the header manually if presen= t. > + > + let current_offset =3D if signature =3D=3D NV_PBUS_IFR_FMT_FIXED= 0_SIGNATURE_VALUE { > + let fixed1 =3D IfrFixed1(bar0.try_read32(ROM_OFFSET + NV_PBU= S_IFR_FMT_FIXED1)?); > + > + match fixed1.version() { > + // Note: We do not actually expect to see v1 or v2 on th= ese GPUs > + 1 | 2 =3D> { > + let fixed_data_size =3D fixed1.fixed_data_size() as = usize; > + let pmgr_rom_addr_offset =3D fixed_data_size + IFR_S= W_EXT_ROM_ADDR_OFFSET; > + bar0.try_read32(ROM_OFFSET + pmgr_rom_addr_offset)? = as usize > + } > + 3 =3D> { > + let fixed2 =3D IfrFixed2(bar0.try_read32(ROM_OFFSET = + NV_PBUS_IFR_FMT_FIXED2)?); > + let total_data_size =3D fixed2.total_data_size() as = usize; > + let dir_offset =3D bar0.try_read32(ROM_OFFSET + tota= l_data_size)? as usize > + + RFW_FLASH_STATUS_SIZE; > + let dir_sig =3D bar0.try_read32(ROM_OFFSET + dir_off= set)?; > + if dir_sig !=3D NV_ROM_DIRECTORY_IDENTIFIER { > + dev_err!(dev, "could not find IFR ROM directory\= n"); > + return Err(EINVAL); > + } > + bar0.try_read32(ROM_OFFSET + dir_offset + 8)? as usi= ze > + } > + _ =3D> { > + dev_err!(dev, "unsupported IFR header version {}\n",= fixed1.version()); > + return Err(EINVAL); > + } > + } > + } else { > + 0 > + }; > + > Ok(Self { > dev, > bar0, > data: KVec::new(), > - current_offset: 0, > + current_offset, > last_found: false, > }) > }