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charset=UTF-8 Date: Mon, 20 Apr 2026 10:28:32 +0900 Message-Id: Cc: "Timur Tabi" , "Danilo Krummrich" , "John Hubbard" , "Joel Fernandes" , "Eliot Courtney" , Subject: Re: [PATCH v5 4/6] gpu: nova-core: add FbHal::frts_size() for GA100 support From: "Alexandre Courbot" To: "Gary Guo" References: <20260417191359.1307434-1-ttabi@nvidia.com> <20260417191359.1307434-5-ttabi@nvidia.com> In-Reply-To: X-ClientProxiedBy: TY4PR01CA0005.jpnprd01.prod.outlook.com (2603:1096:405:26e::8) To CH2PR12MB3990.namprd12.prod.outlook.com (2603:10b6:610:28::18) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH2PR12MB3990:EE_|BN7PPF915F74166:EE_ X-MS-Office365-Filtering-Correlation-Id: 873b8ba1-fc3c-42a7-de0e-08de9e7c2479 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|1800799024|376014|10070799003|18002099003|22082099003|56012099003; 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GA100 is a special case in that there is no FRTS, and so >> the size must be set to 0. >> >> Note that we cannot use supports_display() to determine the FRTS >> size because there are other GPUs (e.g. GA102GL) that have display >> disabled (and so supports_display() returns False), but the FRTS >> window size still needs to be 1MB. >> >> Signed-off-by: Timur Tabi >> Reviewed-by: Eliot Courtney >> --- >> drivers/gpu/nova-core/fb.rs | 6 +++--- >> drivers/gpu/nova-core/fb/hal.rs | 3 +++ >> drivers/gpu/nova-core/fb/hal/ga100.rs | 6 ++++++ >> drivers/gpu/nova-core/fb/hal/ga102.rs | 4 ++++ >> drivers/gpu/nova-core/fb/hal/tu102.rs | 11 ++++++++++- >> 5 files changed, 26 insertions(+), 4 deletions(-) >> >> diff --git a/drivers/gpu/nova-core/fb.rs b/drivers/gpu/nova-core/fb.rs >> index f357fb28b22c..a305a6dac758 100644 >> --- a/drivers/gpu/nova-core/fb.rs >> +++ b/drivers/gpu/nova-core/fb.rs >> @@ -216,10 +216,10 @@ pub(crate) fn new(chipset: Chipset, bar: &Bar0, gs= p_fw: &GspFirmware) -> Result< >> =20 >> let frts =3D { >> const FRTS_DOWN_ALIGN: Alignment =3D Alignment::new::(); >> - const FRTS_SIZE: u64 =3D usize_as_u64(SZ_1M); >> - let frts_base =3D vga_workspace.start.align_down(FRTS_DOWN_= ALIGN) - FRTS_SIZE; >> + let frts_size: u64 =3D hal.frts_size(); >> + let frts_base =3D vga_workspace.start.align_down(FRTS_DOWN_= ALIGN) - frts_size; >> =20 >> - FbRange(frts_base..frts_base + FRTS_SIZE) >> + FbRange(frts_base..frts_base + frts_size) >> }; >> =20 >> let boot =3D { >> diff --git a/drivers/gpu/nova-core/fb/hal.rs b/drivers/gpu/nova-core/fb/= hal.rs >> index aba0abd8ee00..1c01a6cbed65 100644 >> --- a/drivers/gpu/nova-core/fb/hal.rs >> +++ b/drivers/gpu/nova-core/fb/hal.rs >> @@ -25,6 +25,9 @@ pub(crate) trait FbHal { >> =20 >> /// Returns the VRAM size, in bytes. >> fn vidmem_size(&self, bar: &Bar0) -> u64; >> + >> + /// Returns the FRTS size, in bytes. >> + fn frts_size(&self) -> u64; >> } >> =20 >> /// Returns the HAL corresponding to `chipset`. >> diff --git a/drivers/gpu/nova-core/fb/hal/ga100.rs b/drivers/gpu/nova-co= re/fb/hal/ga100.rs >> index 1c03783cddef..2f5871d915c3 100644 >> --- a/drivers/gpu/nova-core/fb/hal/ga100.rs >> +++ b/drivers/gpu/nova-core/fb/hal/ga100.rs >> @@ -66,6 +66,12 @@ fn supports_display(&self, bar: &Bar0) -> bool { >> fn vidmem_size(&self, bar: &Bar0) -> u64 { >> super::tu102::vidmem_size_gp102(bar) >> } >> + >> + // GA100 is a special case where its FRTS region exists, but is emp= ty. We >> + // return a size of 0 because we still need to record where the reg= ion starts. >> + fn frts_size(&self) -> u64 { >> + 0 >> + } >> } >> =20 >> const GA100: Ga100 =3D Ga100; >> diff --git a/drivers/gpu/nova-core/fb/hal/ga102.rs b/drivers/gpu/nova-co= re/fb/hal/ga102.rs >> index 4b9f0f74d0e7..3bb66f64bef7 100644 >> --- a/drivers/gpu/nova-core/fb/hal/ga102.rs >> +++ b/drivers/gpu/nova-core/fb/hal/ga102.rs >> @@ -35,6 +35,10 @@ fn supports_display(&self, bar: &Bar0) -> bool { >> fn vidmem_size(&self, bar: &Bar0) -> u64 { >> vidmem_size_ga102(bar) >> } >> + >> + fn frts_size(&self) -> u64 { >> + super::tu102::frts_size_tu102() > > I checked the patch history and it looks like this changes from v1 to v2.= If the > argument that "both have the same size" then I think this just makes thin= g more > confusing then the purpose of deduplicating. > > All the methods above are either delegating to GA100 code or custom, and = now > this delegates to TU102 without any explanation. The reason for this is that all chips have the same FRTS region size, *except* GA100 which is 0. GA100 is the exception (it is also documented as you can see in its snippet above) and should be treated as such. Thus I'd say the current approach is correct.