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charset=UTF-8 Date: Mon, 01 Jun 2026 16:33:50 +0900 Message-Id: From: "Eliot Courtney" To: "John Hubbard" , "Danilo Krummrich" , "Alexandre Courbot" Cc: "Joel Fernandes" , "Timur Tabi" , "Alistair Popple" , "Eliot Courtney" , "Shashank Sharma" , "Zhi Wang" , "David Airlie" , "Simona Vetter" , "Bjorn Helgaas" , "Miguel Ojeda" , "Alex Gaynor" , "Boqun Feng" , "Gary Guo" , =?utf-8?q?Bj=C3=B6rn_Roy_Baron?= , "Benno Lossin" , "Andreas Hindborg" , "Alice Ryhl" , "Trevor Gross" , , "LKML" Subject: Re: [PATCH v11 06/22] gpu: nova-core: Blackwell: use correct sysmem flush registers X-Mailer: aerc 0.21.0-0-g5549850facc2 References: <20260530030953.740561-1-jhubbard@nvidia.com> <20260530030953.740561-7-jhubbard@nvidia.com> In-Reply-To: <20260530030953.740561-7-jhubbard@nvidia.com> X-ClientProxiedBy: TY4PR01CA0078.jpnprd01.prod.outlook.com (2603:1096:405:36c::16) To BL0PR12MB2353.namprd12.prod.outlook.com (2603:10b6:207:4c::31) Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL0PR12MB2353:EE_|DS0PR12MB7995:EE_ X-MS-Office365-Filtering-Correlation-Id: 85979da8-7341-4bbc-4cf2-08debfb0227c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|366016|10070799003|7416014|376014|1800799024|18002099003|22082099003|4143699003|11063799006|56012099006|6133799003; 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GB10x routes the flush through a pair of HSHUB0 > register sets (primary and egress) that must both be programmed to > the same address. GB20x routes it through FBHUB0. > > Implement these paths in the GB10x and GB20x framebuffer HALs. > > Signed-off-by: John Hubbard > --- > drivers/gpu/nova-core/fb/hal/gb100.rs | 46 +++++++++++++++++++++++++-- > drivers/gpu/nova-core/fb/hal/gb202.rs | 40 +++++++++++++++++++++-- > drivers/gpu/nova-core/regs.rs | 37 +++++++++++++++++++++ > 3 files changed, 117 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/nova-core/fb/hal/gb100.rs b/drivers/gpu/nova-cor= e/fb/hal/gb100.rs > index 8d63350abf8a..70f4c11b1e77 100644 > --- a/drivers/gpu/nova-core/fb/hal/gb100.rs > +++ b/drivers/gpu/nova-core/fb/hal/gb100.rs > @@ -4,6 +4,8 @@ > //! Blackwell GB10x framebuffer HAL. > =20 > use kernel::{ > + io::Io, > + num::Bounded, > prelude::*, > ptr::{ > const_align_up, > @@ -15,11 +17,45 @@ > use crate::{ > driver::Bar0, > fb::hal::FbHal, > - num::usize_into_u32, // > + num::usize_into_u32, > + regs, // > }; > =20 > struct Gb100; > =20 > +fn read_sysmem_flush_page_gb100(bar: &Bar0) -> u64 { > + let lo =3D u64::from( > + bar.read(regs::NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO) > + .adr(), > + ); > + let hi =3D u64::from( > + bar.read(regs::NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI) > + .adr(), > + ); > + > + lo | (hi << 32) > +} > + > +/// Write the sysmem flush page address through the GB10x HSHUB0 registe= rs. > +/// > +/// Both the primary and EG (egress) register pairs must be programmed t= o the same address, > +/// as required by hardware. > +fn write_sysmem_flush_page_gb100(bar: &Bar0, addr: Bounded) { > + // CAST: lower 32 bits. Hardware ignores bits 7:0. > + let addr_lo =3D *addr as u32; > + let addr_hi =3D addr.shr::<32, 20>().cast::(); > + > + // Write HI first. The hardware will trigger the flush on the LO wri= te. > + > + // Primary HSHUB pair. > + bar.write_reg(regs::NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed(= ).with_adr(addr_hi)); > + bar.write_reg(regs::NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed(= ).with_adr(addr_lo)); > + > + // EG (egress) pair -- must match the primary pair. > + bar.write_reg(regs::NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_HI::zero= ed().with_adr(addr_hi)); > + bar.write_reg(regs::NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_LO::zero= ed().with_adr(addr_lo)); > +} > + > pub(super) const fn pmu_reserved_size_gb100() -> u32 { > usize_into_u32::<{ const_align_up(SZ_8M + SZ_16M + SZ_4K, Alignment:= :new::()).unwrap() }>( > ) > @@ -27,11 +63,15 @@ pub(super) const fn pmu_reserved_size_gb100() -> u32 = { > =20 > impl FbHal for Gb100 { > fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { > - super::ga100::read_sysmem_flush_page_ga100(bar) > + read_sysmem_flush_page_gb100(bar) > } > =20 > fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { > - super::ga100::write_sysmem_flush_page_ga100(bar, addr); > + let addr: Bounded =3D Bounded::::from(addr) > + .try_shrink::<52>() > + .ok_or(EINVAL)?; Maybe more simply written: `let addr =3D Bounded::::try_new(addr).ok_or(EINVAL)?;` > + > + write_sysmem_flush_page_gb100(bar, addr); > =20 > Ok(()) > } > diff --git a/drivers/gpu/nova-core/fb/hal/gb202.rs b/drivers/gpu/nova-cor= e/fb/hal/gb202.rs > index 542c1d7429e9..5a6b815eec3d 100644 > --- a/drivers/gpu/nova-core/fb/hal/gb202.rs > +++ b/drivers/gpu/nova-core/fb/hal/gb202.rs > @@ -4,24 +4,58 @@ > //! Blackwell GB20x framebuffer HAL. > =20 > use kernel::{ > + io::Io, > + num::Bounded, > prelude::*, > sizes::SizeConstants, // > }; > =20 > use crate::{ > driver::Bar0, > - fb::hal::FbHal, // > + fb::hal::FbHal, > + regs, // > }; > =20 > struct Gb202; > =20 > +fn read_sysmem_flush_page_gb202(bar: &Bar0) -> u64 { > + let lo =3D u64::from( > + bar.read(regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO) > + .adr(), > + ); > + let hi =3D u64::from( > + bar.read(regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI) > + .adr(), > + ); > + > + lo | (hi << 32) > +} > + > +/// Write the sysmem flush page address through the GB20x FBHUB0 registe= rs. > +fn write_sysmem_flush_page_gb202(bar: &Bar0, addr: Bounded) { > + // Write HI first. The hardware will trigger the flush on the LO wri= te. > + bar.write_reg( > + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI::zeroed() > + .with_adr(addr.shr::<32, 20>().cast::()), > + ); > + bar.write_reg( > + regs::NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO::zeroed() > + // CAST: lower 32 bits. Hardware ignores bits 7:0. > + .with_adr(*addr as u32), > + ); > +} > + > impl FbHal for Gb202 { > fn read_sysmem_flush_page(&self, bar: &Bar0) -> u64 { > - super::ga100::read_sysmem_flush_page_ga100(bar) > + read_sysmem_flush_page_gb202(bar) > } > =20 > fn write_sysmem_flush_page(&self, bar: &Bar0, addr: u64) -> Result { > - super::ga100::write_sysmem_flush_page_ga100(bar, addr); > + let addr: Bounded =3D Bounded::::from(addr) > + .try_shrink::<52>() > + .ok_or(EINVAL)?; Same here. > + > + write_sysmem_flush_page_gb202(bar, addr); > =20 > Ok(()) > } > diff --git a/drivers/gpu/nova-core/regs.rs b/drivers/gpu/nova-core/regs.r= s > index 356fbf364ea5..65be6ec71ed4 100644 > --- a/drivers/gpu/nova-core/regs.rs > +++ b/drivers/gpu/nova-core/regs.rs > @@ -1,4 +1,5 @@ > // SPDX-License-Identifier: GPL-2.0 > +// SPDX-FileCopyrightText: Copyright (c) 2025-2026 NVIDIA CORPORATION & = AFFILIATES. All rights reserved. > =20 > use kernel::{ > io::{ > @@ -145,6 +146,42 @@ fn fmt(&self, f: &mut kernel::fmt::Formatter<'_>) ->= kernel::fmt::Result { > /// Bits 12..40 of the higher (exclusive) bound of the WPR2 regi= on. > 31:4 hi_val; > } > + > + // Blackwell GB10x sysmem flush registers (HSHUB0). > + // > + // GB10x GPUs use two pairs of HSHUB registers for sysmembar: a prim= ary pair and an EG > + // (egress) pair. Both must be programmed to the same address. Hardw= are ignores bits 7:0 > + // of each LO register. HSHUB0 base is 0x00891000. > + > + pub(crate) NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x00891e50= { > + 31:0 adr =3D> u32; > + } > + > + pub(crate) NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00891e54= { > + 19:0 adr; > + } > + > + pub(crate) NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x00891= 6c0 { > + 31:0 adr =3D> u32; > + } > + > + pub(crate) NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00891= 6c4 { > + 19:0 adr; > + } > + > + // Blackwell GB20x sysmem flush registers (FBHUB0). > + // > + // Unlike the older NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers which en= code the address with an > + // 8-bit right-shift, these registers take the raw address split int= o lower/upper 32-bit halves. > + // The hardware ignores bits 7:0 of the LO register. > + > + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008a1d58= { > + 31:0 adr =3D> u32; > + } > + > + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008a1d5c= { > + 19:0 adr; > + } > } May be nice to move these to the place (HAL) they are used if they aren't used anywhere else (and reduce visibility). I am also curious about where 0x00891000 comes from.