From: "Alexandre Courbot" <acourbot@nvidia.com>
To: "Eliot Courtney" <ecourtney@nvidia.com>
Cc: "John Hubbard" <jhubbard@nvidia.com>,
"Danilo Krummrich" <dakr@kernel.org>,
"Joel Fernandes" <joelagnelf@nvidia.com>,
"Timur Tabi" <ttabi@nvidia.com>,
"Alistair Popple" <apopple@nvidia.com>,
"Shashank Sharma" <shashanks@nvidia.com>,
"Zhi Wang" <zhiw@nvidia.com>, "David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Miguel Ojeda" <ojeda@kernel.org>,
"Alex Gaynor" <alex.gaynor@gmail.com>,
"Boqun Feng" <boqun.feng@gmail.com>,
"Gary Guo" <gary@garyguo.net>,
"Björn Roy Baron" <bjorn3_gh@protonmail.com>,
"Benno Lossin" <lossin@kernel.org>,
"Andreas Hindborg" <a.hindborg@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"Trevor Gross" <tmgross@umich.edu>,
rust-for-linux@vger.kernel.org,
LKML <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v11 06/22] gpu: nova-core: Blackwell: use correct sysmem flush registers
Date: Mon, 01 Jun 2026 22:13:20 +0900 [thread overview]
Message-ID: <DIXQMLMN7RQO.1OUEPLVALLMXK@nvidia.com> (raw)
In-Reply-To: <DIXJEO0ILZVH.2BOQ4HKC3396B@nvidia.com>
On Mon Jun 1, 2026 at 4:33 PM JST, Eliot Courtney wrote:
> On Sat May 30, 2026 at 12:09 PM JST, John Hubbard wrote:
>> +
>> + // Blackwell GB10x sysmem flush registers (HSHUB0).
>> + //
>> + // GB10x GPUs use two pairs of HSHUB registers for sysmembar: a primary pair and an EG
>> + // (egress) pair. Both must be programmed to the same address. Hardware ignores bits 7:0
>> + // of each LO register. HSHUB0 base is 0x00891000.
>> +
>> + pub(crate) NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x00891e50 {
>> + 31:0 adr => u32;
>> + }
>> +
>> + pub(crate) NV_PFB_HSHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x00891e54 {
>> + 19:0 adr;
>> + }
>> +
>> + pub(crate) NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008916c0 {
>> + 31:0 adr => u32;
>> + }
>> +
>> + pub(crate) NV_PFB_HSHUB0_EG_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008916c4 {
>> + 19:0 adr;
>> + }
>> +
>> + // Blackwell GB20x sysmem flush registers (FBHUB0).
>> + //
>> + // Unlike the older NV_PFB_NISO_FLUSH_SYSMEM_ADDR registers which encode the address with an
>> + // 8-bit right-shift, these registers take the raw address split into lower/upper 32-bit halves.
>> + // The hardware ignores bits 7:0 of the LO register.
>> +
>> + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_LO(u32) @ 0x008a1d58 {
>> + 31:0 adr => u32;
>> + }
>> +
>> + pub(crate) NV_PFB_FBHUB0_PCIE_FLUSH_SYSMEM_ADDR_HI(u32) @ 0x008a1d5c {
>> + 19:0 adr;
>> + }
>> }
>
> May be nice to move these to the place (HAL) they are used if they
> aren't used anywhere else (and reduce visibility).
Indeed, we have a thread on Zulip [1] suggesting to move register
definitions into subdevice-level `regs.rs` modules. I guess we could
proactively start doing this with these new registers; on the other
hand, I'm also fine with keeping the current pattern and doing the move
later if John prefers to keep things the current way.
[1] https://rust-for-linux.zulipchat.com/#narrow/channel/509436-Nova/topic/.5BRFC.5D.20Moving.20register.20definitions.20into.20the.20module.20using.20them/with/599138666
next prev parent reply other threads:[~2026-06-01 13:13 UTC|newest]
Thread overview: 56+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-30 3:09 [PATCH v11 00/22] gpu: nova-core: firmware: Hopper/Blackwell support John Hubbard
2026-05-30 3:09 ` [PATCH v11 01/22] gpu: nova-core: set DMA mask width based on GPU architecture John Hubbard
2026-06-01 4:01 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 02/22] gpu: nova-core: Hopper/Blackwell: new location for PCI config mirror John Hubbard
2026-06-01 4:04 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 03/22] gpu: nova-core: Blackwell: compute PMU-reserved framebuffer size John Hubbard
2026-06-01 2:07 ` Alexandre Courbot
2026-06-01 5:34 ` Alexandre Courbot
2026-06-01 18:01 ` John Hubbard
2026-06-01 4:41 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 04/22] gpu: nova-core: Hopper/Blackwell: larger non-WPR heap John Hubbard
2026-06-01 2:24 ` Alexandre Courbot
2026-06-01 18:03 ` John Hubbard
2026-06-01 5:01 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 05/22] gpu: nova-core: Hopper/Blackwell: larger WPR2 (GSP) heap John Hubbard
2026-06-01 5:21 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 06/22] gpu: nova-core: Blackwell: use correct sysmem flush registers John Hubbard
2026-06-01 7:01 ` Alexandre Courbot
2026-06-01 18:16 ` John Hubbard
2026-06-01 7:33 ` Eliot Courtney
2026-06-01 13:13 ` Alexandre Courbot [this message]
2026-06-01 18:09 ` John Hubbard
2026-05-30 3:09 ` [PATCH v11 07/22] gpu: nova-core: don't assume 64-bit firmware images John Hubbard
2026-06-01 6:36 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 08/22] gpu: nova-core: add support for 32-bit " John Hubbard
2026-06-01 6:37 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 09/22] gpu: nova-core: add auto-detection of 32-bit, 64-bit " John Hubbard
2026-06-01 6:49 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 10/22] gpu: nova-core: Hopper/Blackwell: add FSP falcon engine stub John Hubbard
2026-06-01 7:47 ` Eliot Courtney
2026-06-01 16:10 ` Timur Tabi
2026-06-01 18:17 ` John Hubbard
2026-05-30 3:09 ` [PATCH v11 11/22] gpu: nova-core: Hopper/Blackwell: add FMC firmware image John Hubbard
2026-06-01 8:38 ` Eliot Courtney
2026-05-30 3:09 ` [PATCH v11 12/22] gpu: nova-core: Hopper/Blackwell: add FSP secure boot completion waiting John Hubbard
2026-06-01 7:48 ` Alexandre Courbot
2026-06-01 8:32 ` Eliot Courtney
2026-06-01 13:07 ` Alexandre Courbot
2026-06-01 18:18 ` John Hubbard
2026-05-30 3:09 ` [PATCH v11 13/22] gpu: nova-core: Hopper/Blackwell: add FMC signature extraction John Hubbard
2026-06-01 8:55 ` Eliot Courtney
2026-06-01 14:45 ` Alexandre Courbot
2026-06-01 14:49 ` Alexandre Courbot
2026-06-01 18:21 ` John Hubbard
2026-05-30 3:09 ` [PATCH v11 14/22] gpu: nova-core: Hopper/Blackwell: add FSP falcon EMEM operations John Hubbard
2026-05-30 3:09 ` [PATCH v11 15/22] gpu: nova-core: Hopper/Blackwell: add FSP message infrastructure John Hubbard
2026-05-30 3:09 ` [PATCH v11 16/22] gpu: nova-core: add MCTP/NVDM protocol types for firmware communication John Hubbard
2026-05-30 3:09 ` [PATCH v11 17/22] gpu: nova-core: Hopper/Blackwell: add FSP send/receive messaging John Hubbard
2026-05-30 3:09 ` [PATCH v11 18/22] gpu: nova-core: Hopper/Blackwell: add FspCotVersion type John Hubbard
2026-06-01 14:07 ` Alexandre Courbot
2026-06-01 18:23 ` John Hubbard
2026-05-30 3:09 ` [PATCH v11 19/22] gpu: nova-core: Hopper/Blackwell: add FSP Chain of Trust boot John Hubbard
2026-05-30 3:09 ` [PATCH v11 20/22] gpu: nova-core: Hopper/Blackwell: add GSP lockdown release polling John Hubbard
2026-05-30 3:09 ` [PATCH v11 21/22] gpu: nova-core: add non-sec2 unload path John Hubbard
2026-05-30 3:09 ` [PATCH v11 22/22] gpu: nova-core: gsp: enable FSP boot path John Hubbard
2026-05-30 3:21 ` [PATCH v11 00/22] gpu: nova-core: firmware: Hopper/Blackwell support John Hubbard
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