From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id DFC022F365B; Wed, 2 Jul 2025 15:21:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751469669; cv=none; b=MoxZH+q+y4A2vJYAqfclfvcgvMYH15Y8DO2i4Va4YKPyA7a88IU9FtDcFktBhmqR5ID2/tBZqS0dEbsW0nfK389DVvR6OMr+gqKwMz0G1XzDjrHEpKHUbnSd1Liha8wLYec89Bz1aX8HZhLGU6yNvIFfSx6syyyLr3C52H2i2b8= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751469669; c=relaxed/simple; bh=M/1qI026Rf8MHuDJoLIxqcQbHcw9InNMCIRG1daBlW4=; h=Date:From:To:Cc:Subject:Message-ID:References:MIME-Version: Content-Type:Content-Disposition:In-Reply-To; b=gS6C02ukT/m718ZBuT2daezwc3+RWT/FVyB4zXKG8qjf4UW7U43xdoEeXC0WVyA16njWTE6R77Ccn6cjCLn2DfMJhb6lh0dffqYm/MFsidnv2BMzN1FbgNBJoMxrH50xL0PSRdK+NK31rY2Ds8wY+tVIauA655yfDzlmKXQwsN0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=gt1ABjjI; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="gt1ABjjI" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6A127C4CEE7; Wed, 2 Jul 2025 15:21:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751469668; bh=M/1qI026Rf8MHuDJoLIxqcQbHcw9InNMCIRG1daBlW4=; h=Date:From:To:Cc:Subject:References:In-Reply-To:From; b=gt1ABjjID7Yl1S93DXNEXXx9Gu+slXGI3XlUkze9+VdPfBrRji29vH/Za7ojXIyJc NoY/8Kk5iCroXeRw/044bIbHoRswoHsJy00tTHMdd1NAnNLUdJg0rNQvTJQNRoa9Vk oEjZWsS/9UOnwcmtp+bEdcCepAJJ1B4kb1zCN2LG1SUT3mtc2IoqUnW2p1WwAm+aBU kUKnxBuGnEEuO9FWQHj+ewubg6e7wXbxE7icOT9PkwujBlhN8Kwtdx2p0aFiwVd+FD rthuZtHy4zRT/tsB04nNnve7FTpvTj7Q0Dppc1lF1c4kvsndaOBiafeh1s4WRaKNNR dih7Dip1xrTLg== Date: Wed, 2 Jul 2025 17:21:00 +0200 From: Danilo Krummrich To: Michal Wilczynski Cc: Uwe =?iso-8859-1?Q?Kleine-K=F6nig?= , Miguel Ojeda , Alex Gaynor , Boqun Feng , Gary Guo , =?iso-8859-1?Q?Bj=F6rn?= Roy Baron , Andreas Hindborg , Alice Ryhl , Trevor Gross , Guo Ren , Fu Wei , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Marek Szyprowski , Benno Lossin , Michael Turquette , Drew Fustini , linux-kernel@vger.kernel.org, linux-pwm@vger.kernel.org, rust-for-linux@vger.kernel.org, linux-riscv@lists.infradead.org, devicetree@vger.kernel.org Subject: Re: [PATCH v7 4/8] rust: pwm: Add driver operations trait and registration support Message-ID: References: <20250702-rust-next-pwm-working-fan-for-sending-v7-0-67ef39ff1d29@samsung.com> <20250702-rust-next-pwm-working-fan-for-sending-v7-4-67ef39ff1d29@samsung.com> Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250702-rust-next-pwm-working-fan-for-sending-v7-4-67ef39ff1d29@samsung.com> On Wed, Jul 02, 2025 at 03:45:32PM +0200, Michal Wilczynski wrote: > +impl Registration { > + /// Registers a PWM chip with the PWM subsystem. > + /// > + /// Transfers its ownership to the `devres` framework, which ties its lifetime > + /// to the parent device. > + /// On unbind of the parent device, the `devres` entry will be dropped, automatically > + /// calling `pwmchip_remove`. This function should be called from the driver's `probe`. > + pub fn register( > + dev: &device::Device, > + chip: ARef, > + ops_vtable: &'static PwmOpsVTable, > + ) -> Result { One thing I did miss here: Given that this should give us the guarantee that the parent device of the Chip is always bound, you have to add a check for this here, i.e. fail if `dev.as_raw() != chip.parent().as_raw()`. > + let c_chip_ptr = chip.as_raw(); > + > + // SAFETY: `c_chip_ptr` is valid because the `ARef` that owns it exists. > + // The vtable pointer is also valid. This sets the `.ops` field on the C struct. > + unsafe { > + (*c_chip_ptr).ops = ops_vtable.as_raw(); > + } > + > + // SAFETY: `c_chip_ptr` points to a valid chip with its ops initialized. > + // `__pwmchip_add` is the C function to register the chip with the PWM core. > + unsafe { > + to_result(bindings::__pwmchip_add(c_chip_ptr, core::ptr::null_mut()))?; > + } > + > + let registration = Registration { chip }; > + > + devres::register(dev, registration, GFP_KERNEL) > + } > +}