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[103.168.172.201]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4e881c8a20csm59703181cf.16.2025.10.16.23.48.26 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 16 Oct 2025 23:48:27 -0700 (PDT) Received: from phl-compute-08.internal (phl-compute-08.internal [10.202.2.48]) by mailfauth.phl.internal (Postfix) with ESMTP id 272D8F4006A; Fri, 17 Oct 2025 02:48:26 -0400 (EDT) Received: from phl-mailfrontend-01 ([10.202.2.162]) by phl-compute-08.internal (MEProxy); Fri, 17 Oct 2025 02:48:26 -0400 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeeffedrtdeggdduvdekgeelucetufdoteggodetrf dotffvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfurfetoffkrfgpnffqhgenuceu rghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujf gurhepfffhvfevuffkfhggtggujgesthdtredttddtvdenucfhrhhomhepuehoqhhunhcu hfgvnhhguceosghoqhhunhdrfhgvnhhgsehgmhgrihhlrdgtohhmqeenucggtffrrghtth gvrhhnpeehudfgudffffetuedtvdehueevledvhfelleeivedtgeeuhfegueevieduffei vdenucevlhhushhtvghrufhiiigvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegsoh hquhhnodhmvghsmhhtphgruhhthhhpvghrshhonhgrlhhithihqdeiledvgeehtdeigedq udejjeekheehhedvqdgsohhquhhnrdhfvghngheppehgmhgrihhlrdgtohhmsehfihigmh gvrdhnrghmvgdpnhgspghrtghpthhtohepfedvpdhmohguvgepshhmthhpohhuthdprhgt phhtthhopegurghvihgurdhlrghighhhthdrlhhinhhugiesghhmrghilhdrtghomhdprh gtphhtthhopehlhihuuggvsehrvgguhhgrthdrtghomhdprhgtphhtthhopehruhhsthdq fhhorhdqlhhinhhugiesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehtgh hlgieslhhinhhuthhrohhnihigrdguvgdprhgtphhtthhopehlihhnuhigqdhkvghrnhgv lhesvhhgvghrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopegurghnihgvlhdrrghlmh gvihgurgestgholhhlrggsohhrrgdrtghomhdprhgtphhtthhopehmihhnghhosehrvggu hhgrthdrtghomhdprhgtphhtthhopehpvghtvghriiesihhnfhhrrgguvggrugdrohhrgh dprhgtphhtthhopehjuhhrihdrlhgvlhhlihesrhgvughhrghtrdgtohhm X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Fri, 17 Oct 2025 02:48:25 -0400 (EDT) Date: Thu, 16 Oct 2025 23:48:24 -0700 From: Boqun Feng To: David Laight Cc: Lyude Paul , rust-for-linux@vger.kernel.org, Thomas Gleixner , linux-kernel@vger.kernel.org, Daniel Almeida , Ingo Molnar , Peter Zijlstra , Juri Lelli , Vincent Guittot , Dietmar Eggemann , Steven Rostedt , Ben Segall , Mel Gorman , Valentin Schneider , Will Deacon , Waiman Long , Miguel Ojeda , Alex Gaynor , Gary Guo , =?iso-8859-1?Q?Bj=F6rn?= Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , David Woodhouse , Sebastian Andrzej Siewior , Joel Fernandes , Ryo Takakura , K Prateek Nayak Subject: Re: [PATCH v13 05/17] irq & spin_lock: Add counted interrupt disabling/enabling Message-ID: References: <20251013155205.2004838-1-lyude@redhat.com> <20251013155205.2004838-6-lyude@redhat.com> <20251016222421.512ca8d1@pumpkin> Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251016222421.512ca8d1@pumpkin> On Thu, Oct 16, 2025 at 10:24:21PM +0100, David Laight wrote: > On Mon, 13 Oct 2025 11:48:07 -0400 > Lyude Paul wrote: > > > From: Boqun Feng > > > > Currently the nested interrupt disabling and enabling is present by > > _irqsave() and _irqrestore() APIs, which are relatively unsafe, for > > example: > > > > > > spin_lock_irqsave(l1, flag1); > > spin_lock_irqsave(l2, flag2); > > spin_unlock_irqrestore(l1, flags1); > > > > // accesses to interrupt-disable protect data will cause races. > > To do this right you have to correctly 'nest' the flags even though > the locks are chained. > So you should have: > spin_unlock_irqrestore(l1, flags2); > Which is one reason why schemes that save the interrupt state in the > lock are completely broken. > > Did you consider a scheme where the interrupt disable count is held in a > per-cpu variable (rather than on-stack)? > It might have to be the same per-cpu variable that is used for disabling > pre-emption. > If you add (say) 256 to disable interrupts and do the hardware disable > when the count ends up between 256 and 511 and the enable on the opposite > transition I think it should work. > An interrupt after the increment will be fine - it can't do a process > switch. > This patch is exactly about using percpu (in this case it's the preempt count) to track interrupt disabling nested level and enabling interrupts when the count reaches to 0 ;-) Regards, Boqun > The read-add-write doesn't even need to be atomic. > The problem is a process switch and that can only happen when the only > value is zero - so it doesn't matter it is can from a different cpu! > > I know some systems (I think including x86) have only incremented such a > counter instead of doing the hardware interrupt disable. > When an interrupt happens they realise it shouldn't have, block the IRQ, > remember there is a deferred interrupt, and return from the ISR. > This is good for very short disables - because the chance of an IRQ > is low. > > David >