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[103.168.172.201]) by smtp.gmail.com with ESMTPSA id d75a77b69052e-4f4ac62fa56sm190298711cf.17.2025.12.26.23.23.35 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 26 Dec 2025 23:23:36 -0800 (PST) Received: from phl-compute-01.internal (phl-compute-01.internal [10.202.2.41]) by mailfauth.phl.internal (Postfix) with ESMTP id 78603F40068; Sat, 27 Dec 2025 02:23:35 -0500 (EST) Received: from phl-frontend-03 ([10.202.2.162]) by phl-compute-01.internal (MEProxy); Sat, 27 Dec 2025 02:23:35 -0500 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeefgedrtddtgdejtdejhecutefuodetggdotefrod ftvfcurfhrohhfihhlvgemucfhrghsthforghilhdpuffrtefokffrpgfnqfghnecuuegr ihhlohhuthemuceftddtnecusecvtfgvtghiphhivghnthhsucdlqddutddtmdenucfjug hrpeffhffvvefukfhfgggtuggjsehttdertddttddvnecuhfhrohhmpeeuohhquhhnucfh vghnghcuoegsohhquhhnrdhfvghnghesghhmrghilhdrtghomheqnecuggftrfgrthhtvg hrnhephfetvdfgtdeukedvkeeiteeiteejieehvdetheduudejvdektdekfeegvddvhedt necuffhomhgrihhnpehkvghrnhgvlhdrohhrghenucevlhhushhtvghrufhiiigvpedtne curfgrrhgrmhepmhgrihhlfhhrohhmpegsohhquhhnodhmvghsmhhtphgruhhthhhpvghr shhonhgrlhhithihqdeiledvgeehtdeigedqudejjeekheehhedvqdgsohhquhhnrdhfvg hngheppehgmhgrihhlrdgtohhmsehfihigmhgvrdhnrghmvgdpnhgspghrtghpthhtohep udefpdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehfuhhjihhtrgdrthhomhhonh horhhisehgmhgrihhlrdgtohhmpdhrtghpthhtohepghgrrhihsehgrghrhihguhhordhn vghtpdhrtghpthhtohepohhjvggurgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtoheprg drhhhinhgusghorhhgsehkvghrnhgvlhdrohhrghdprhgtphhtthhopegrlhhitggvrhih hhhlsehgohhoghhlvgdrtghomhdprhgtphhtthhopegsjhhorhhnfegpghhhsehprhhoth honhhmrghilhdrtghomhdprhgtphhtthhopegurghkrheskhgvrhhnvghlrdhorhhgpdhr tghpthhtoheplhhoshhsihhnsehkvghrnhgvlhdrohhrghdprhgtphhtthhopehtmhhgrh hoshhssehumhhitghhrdgvughu X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Sat, 27 Dec 2025 02:23:34 -0500 (EST) Date: Sat, 27 Dec 2025 15:23:30 +0800 From: Boqun Feng To: FUJITA Tomonori Cc: gary@garyguo.net, ojeda@kernel.org, a.hindborg@kernel.org, aliceryhl@google.com, bjorn3_gh@protonmail.com, dakr@kernel.org, lossin@kernel.org, tmgross@umich.edu, acourbot@nvidia.com, rust-for-linux@vger.kernel.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v2 0/4] rust: Add i8/i16 atomic xchg helpers Message-ID: References: <20251223062140.938325-1-fujita.tomonori@gmail.com> <20251223124639.7771082d.gary@garyguo.net> <20251225.095655.275822477142372376.fujita.tomonori@gmail.com> Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20251225.095655.275822477142372376.fujita.tomonori@gmail.com> On Thu, Dec 25, 2025 at 09:56:55AM +0900, FUJITA Tomonori wrote: [...] > >> The architectures supporting Rust, implement atomic xchg families > >> using architecture-specific instructions. They work for i8/i16 too so > >> the helpers just call them. > >> > >> Tested on QEMU (86_64, arm64, riscv, loongarch, and armv7). > >> > >> Note the architectures that support Rust handle xchg differently: > >> > >> - arm64 and riscv support xchg with all the orderings. > >> > >> - x86_64 and loongarch support only full-ordering xchg. They calls the > >> full-ordering xchg for any orderings. > > > > Maybe it's just that I'm reading this differently, but I think this is a > > bit confusing, as if there's an optimisation opportunity. > > > > x86 is TSO, so even a relaxed xchg is a full xchg. So in this sense x86 > > has implemented all orderings. > > For x86_64, I agree that the wording is confusing. xchg always implies > lock so different memory orderings all map to the same full-ordered > xchg there. > I feel a bit confusing as well about the need of mentioning the exact ordering of these primitives on each arch. In my opinion, as long as rust_helper_xchg_X() is mapped to xchg_X() in C, then it's clear that they have the ordering of the corresponding C APIs. But I keep it as it is for now, I may remove them from the commit logs later after I re-think about this. > > > Looking at loongarch ISA manual it's suggested that apart from load/store, > > all other atomic memory instructions are also always full ordering. > > On loongarch there are two possible implementations: an LL/SC-based > one, which is effectively always full-ordered (similar to x86), and an > AMO-based on, where weaker orderings may be possible, as only the AM > variants with the DBAR function appear to be full-ordered. > > > > The change themselves LGTM, so > > > > Reviewed-by: Gary Guo > > Thanks a lot! > Thank you all! Applied in rust-sync: https://git.kernel.org/pub/scm/linux/kernel/git/boqun/linux.git/ rust-sync Regards, Boqun