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[103.168.172.200]) by smtp.gmail.com with ESMTPSA id 6a1803df08f44-8942e6043a6sm117196466d6.18.2026.01.20.13.03.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 20 Jan 2026 13:03:52 -0800 (PST) Received: from phl-compute-08.internal (phl-compute-08.internal [10.202.2.48]) by mailfauth.phl.internal (Postfix) with ESMTP id 33A63F4006D; Tue, 20 Jan 2026 16:03:51 -0500 (EST) Received: from phl-frontend-03 ([10.202.2.162]) by phl-compute-08.internal (MEProxy); Tue, 20 Jan 2026 16:03:51 -0500 X-ME-Sender: X-ME-Received: X-ME-Proxy-Cause: gggruggvucftvghtrhhoucdtuddrgeefgedrtddtgddugedugeegucetufdoteggodetrf dotffvucfrrhhofhhilhgvmecuhfgrshhtofgrihhlpdfurfetoffkrfgpnffqhgenuceu rghilhhouhhtmecufedttdenucesvcftvggtihhpihgvnhhtshculddquddttddmnecujf gurhepfffhvfevuffkfhggtggujgesthdtredttddtvdenucfhrhhomhepuehoqhhunhcu hfgvnhhguceosghoqhhunhdrfhgvnhhgsehgmhgrihhlrdgtohhmqeenucggtffrrghtth gvrhhnpeejiefhtdeuvdegvddtudffgfegfeehgfdtiedvveevleevhfekhefftdekieeh vdenucffohhmrghinheprhhushhtqdhlrghnghdrohhrghenucevlhhushhtvghrufhiii gvpedtnecurfgrrhgrmhepmhgrihhlfhhrohhmpegsohhquhhnodhmvghsmhhtphgruhht hhhpvghrshhonhgrlhhithihqdeiledvgeehtdeigedqudejjeekheehhedvqdgsohhquh hnrdhfvghngheppehgmhgrihhlrdgtohhmsehfihigmhgvrdhnrghmvgdpnhgspghrtghp thhtohepvdekpdhmohguvgepshhmthhpohhuthdprhgtphhtthhopehgrghrhiesghgrrh ihghhuohdrnhgvthdprhgtphhtthhopehruhhsthdqfhhorhdqlhhinhhugiesvhhgvghr rdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehlihhnuhigqdhkvghrnhgvlhesvhhgvg hrrdhkvghrnhgvlhdrohhrghdprhgtphhtthhopehrtghusehvghgvrhdrkhgvrhhnvghl rdhorhhgpdhrtghpthhtohepohhjvggurgeskhgvrhhnvghlrdhorhhgpdhrtghpthhtoh epsghjohhrnhefpghghhesphhrohhtohhnmhgrihhlrdgtohhmpdhrtghpthhtoheplhho shhsihhnsehkvghrnhgvlhdrohhrghdprhgtphhtthhopegrrdhhihhnuggsohhrgheskh gvrhhnvghlrdhorhhgpdhrtghpthhtoheprghlihgtvghrhihhlhesghhoohhglhgvrdgt ohhm X-ME-Proxy: Feedback-ID: iad51458e:Fastmail Received: by mail.messagingengine.com (Postfix) with ESMTPA; Tue, 20 Jan 2026 16:03:50 -0500 (EST) Date: Wed, 21 Jan 2026 05:03:48 +0800 From: Boqun Feng To: Gary Guo Cc: rust-for-linux@vger.kernel.org, linux-kernel@vger.kernel.org, rcu@vger.kernel.org, Miguel Ojeda , =?iso-8859-1?Q?Bj=F6rn?= Roy Baron , Benno Lossin , Andreas Hindborg , Alice Ryhl , Trevor Gross , Danilo Krummrich , Will Deacon , Peter Zijlstra , Mark Rutland , "Paul E. McKenney" , Frederic Weisbecker , Neeraj Upadhyay , Joel Fernandes , Josh Triplett , Uladzislau Rezki , Steven Rostedt , Mathieu Desnoyers , Lai Jiangshan , Zqiang , FUJITA Tomonori , Dirk Behme , Dirk Behme Subject: Re: [PATCH v2 1/2] rust: sync: atomic: Clarify the need of CONFIG_ARCH_SUPPORTS_ATOMIC_RMW Message-ID: References: <20260120140503.62804-1-boqun.feng@gmail.com> <20260120140503.62804-2-boqun.feng@gmail.com> Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: On Tue, Jan 20, 2026 at 04:54:51PM +0000, Gary Guo wrote: > On Tue Jan 20, 2026 at 2:05 PM GMT, Boqun Feng wrote: > > Currently, since all the architectures that support Rust all have > > CONFIG_ARCH_SUPPORTS_ATOMIC_RMW selected, the helpers of atomic > > load/store on i8 and i16 relies on CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=y. > > It's generally fine since most of architectures support that. > > > > The plan for CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=n architectures is adding > > their (probably lock-based) atomic load/store for i8 and i16 as their > > atomic_{read,set}() and atomic64_{read,set}() counterpart when they > > plans to support Rust. > > > > Hence use a statis_assert!() to check this and remind the future us the > > need of the helpers. This is more clear than the #[cfg] on impl blocks > > of i8 and i16. > > > > Suggested-by: Dirk Behme > > Suggested-by: Benno Lossin > > Signed-off-by: Boqun Feng > > Reviewed-by: Gary Guo > Thanks! > > --- > > rust/kernel/sync/atomic/internal.rs | 19 +++++++++++++------ > > 1 file changed, 13 insertions(+), 6 deletions(-) > > > > diff --git a/rust/kernel/sync/atomic/internal.rs b/rust/kernel/sync/atomic/internal.rs > > index 0dac58bca2b3..ef516bcb02ee 100644 > > --- a/rust/kernel/sync/atomic/internal.rs > > +++ b/rust/kernel/sync/atomic/internal.rs > > @@ -37,16 +37,23 @@ pub trait AtomicImpl: Sized + Send + Copy + private::Sealed { > > type Delta; > > } > > > > -// The current helpers of load/store uses `{WRITE,READ}_ONCE()` hence the atomicity is only > > -// guaranteed against read-modify-write operations if the architecture supports native atomic RmW. > > -#[cfg(CONFIG_ARCH_SUPPORTS_ATOMIC_RMW)] > > +// The current helpers of load/store of atomic `i8` and `i16` use `{WRITE,READ}_ONCE()` hence the > > +// atomicity is only guaranteed against read-modify-write operations if the architecture supports > > +// native atomic RmW. > > +// > > +// In the future when a CONFIG_ARCH_SUPPORTS_ATOMIC_RMW=n architecture plans to support Rust, the > > +// load/store helpers that guarantee atomicity against RmW operations (usually via a lock) need to > > +// be added. > > +crate::static_assert!( > > + cfg!(CONFIG_ARCH_SUPPORTS_ATOMIC_RMW), > > + "The current implementation of atomic i8/i16/ptr relies on the architecure being \ > > + ARCH_SUPPORTS_ATOMIC_RMW" > > The printed string when assertion fails will have 5 spaces between "being" and > "ARCH", although it probably doesn't matter.. > Are you sure? My test result shows: ERROR:root:error[E0080]: evaluation panicked: The current implementation of atomic i8/i16/ptr relies on the architecure being ARCH_SUPPORTS_ATOMIC_RMW similar is the following playground example: https://play.rust-lang.org/?version=stable&mode=debug&edition=2024&gist=5dd0098247503be792bc35cda8f2630f Regards, Boqun > Best, > Gary > > > +); > > + > > impl AtomicImpl for i8 { > > type Delta = Self; > > } > > > > -// The current helpers of load/store uses `{WRITE,READ}_ONCE()` hence the atomicity is only > > -// guaranteed against read-modify-write operations if the architecture supports native atomic RmW. > > -#[cfg(CONFIG_ARCH_SUPPORTS_ATOMIC_RMW)] > > impl AtomicImpl for i16 { > > type Delta = Self; > > } >