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AJvYcCXMNZ91D1XuIbIgXNRTG8xcNyNeKRBQyhxV0d4KCKn+9YVmreLzlB1IUR8aVv93tEj7zEAlsbvL1p6QTtS4kQ==@vger.kernel.org X-Gm-Message-State: AOJu0YyjIuKrH3oEBLhkRYVfMuToWv+7PbPMZBOoQqYSCoGH5gxNHzSc GXjV0OPu3eR5XwG9j2s40ho3esr0j6XkCOT+2AQwUhX1ayekMInuAGZWI1+9k0DKO6PMwXAakdP H9sLY03mC1HwFK4SSUA== X-Received: from ejdce41.prod.google.com ([2002:a17:907:d2e9:b0:b8e:7975:1950]) (user=aliceryhl job=prod-delivery.src-stubby-dispatcher) by 2002:a17:907:96a3:b0:b87:8172:257 with SMTP id a640c23a62f3a-b8edf47dd02mr829999966b.64.1770736079025; Tue, 10 Feb 2026 07:07:59 -0800 (PST) Date: Tue, 10 Feb 2026 15:07:58 +0000 In-Reply-To: Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260209155843.725dcfe1@fedora> <20260210101525.7fb85f25@fedora> <20260210133617.0a4be958@fedora> <20260210142631.6f8a3411@fedora> Message-ID: Subject: Re: [RFC PATCH 2/4] rust: sync: Add dma_fence abstractions From: Alice Ryhl To: "Christian =?utf-8?B?S8O2bmln?=" Cc: Boris Brezillon , Philipp Stanner , phasta@kernel.org, Danilo Krummrich , David Airlie , Simona Vetter , Gary Guo , Benno Lossin , Daniel Almeida , Joel Fernandes , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, rust-for-linux@vger.kernel.org Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Tue, Feb 10, 2026 at 02:56:52PM +0100, Christian K=C3=B6nig wrote: > On 2/10/26 14:49, Alice Ryhl wrote: > > On Tue, Feb 10, 2026 at 02:26:31PM +0100, Boris Brezillon wrote: > >> On Tue, 10 Feb 2026 13:15:31 +0000 > >> Alice Ryhl wrote: > >> > >>> On Tue, Feb 10, 2026 at 01:36:17PM +0100, Boris Brezillon wrote: > >>>> On Tue, 10 Feb 2026 10:15:04 +0000 > >>>> Alice Ryhl wrote: > >>>> =20 > >>>>> impl MustBeSignalled<'_> { > >>>>> /// Drivers generally should not use this one. > >>>>> fn i_promise_it_will_be_signalled(self) -> WillBeSignalled { ..= . } > >>>>> > >>>>> /// One way to ensure the fence has been signalled is to signal= it. > >>>>> fn signal_fence(self) -> WillBeSignalled { > >>>>> self.fence.signal(); > >>>>> self.i_promise_it_will_be_signalled() > >>>>> } > >>>>> > >>>>> /// Another way to ensure the fence will be signalled is to spa= wn a > >>>>> /// workqueue item that promises to signal it. > >>>>> fn transfer_to_wq( > >>>>> self, > >>>>> wq: &Workqueue, > >>>>> item: impl DmaFenceWorkItem, > >>>>> ) -> WillBeSignalled { > >>>>> // briefly obtain the lock class of the wq to indicate to > >>>>> // lockdep that the signalling path "blocks" on arbitrary j= obs > >>>>> // from this wq completing > >>>>> bindings::lock_acquire(&wq->key); > >>>>> bindings::lock_release(&wq->key); > >>>>> > >>>>> // enqueue the job > >>>>> wq.enqueue(item, wq); > >>>>> > >>>>> // The signature of DmaFenceWorkItem::run() promises to arr= ange > >>>>> // for it to be signalled. > >>>>> self.i_promise_it_will_be_signalled() > >>>>> } =20 > >>>> > >>>> I guess what's still missing is some sort of `transfer_to_hw()` > >>>> function and way to flag the IRQ handler taking over the fence > >>>> signaling token. =20 > >>> > >>> Yes, transfer to hardware needs to be another piece of logic similar = to > >>> transfer to wq. And I imagine there are many ways such a transfer to > >>> hardware could work. > >>> > >>> Unless you have a timeout on it, in which case the WillBeSignalled is > >>> satisfied by the fact you have a timeout alone, and the signalling th= at > >>> happens from the irq is just an opportunistic signal from outside the > >>> dma fence signalling critical path. > >> > >> Yes and no. If it deadlocks in the completion WorkItem because of > >> allocations (or any of the forbidden use cases), I think we want to > >> catch that, because that's a sign fences are likely to end up with > >> timeouts when they should have otherwise been signaled properly. > >> > >>> Well ... unless triggering timeouts can block on GFP_KERNEL > >>> allocations... > >> > >> I mean, the timeout handler should also be considered a DMA-signalling > >> path, and the same rules should apply to it. > >=20 > > I guess that's fair. Even with a timeout you want both to be signalling > > path. > >=20 > > I guess more generally, if a fence is signalled by mechanism A or B, > > whichever happens first, you have the choice between: >=20 > That doesn't happen in practice. >=20 > For each fence you only have one signaling path you need to guarantee > forward progress for. >=20 > All other signaling paths are just opportunistically optimizations > which *can* signal the fence, but there is no guarantee that they > will. >=20 > We used to have some exceptions to that, especially around aborting > submissions, but those turned out to be a really bad idea as well. =20 >=20 > Thinking more about it you should probably enforce that there is only > one signaling path for each fence signaling. I'm not really convinced by this. First, the timeout path must be a fence signalling path because the reason you have a timeout in the first place is because the hw might never signal the fence. So if the timeout path deadlocks on a kmalloc(GFP_KERNEL) and the hw never comes around to wake you up, boom. Second, for the reasons I mentioned you also want the signal-from-irq path to be a fence signalling critical path, because if we allow you to kmalloc(GFP_KERNEL) on the path from getting notification from hardware to signalling the fence, then you may deadlock until the timeout triggers ... even if the deadlock is only temporary, we should still avoid such cases IMO. Thus, the hw signal path should also be a fence signalling critical path. Alice