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Tue, 7 Apr 2026 05:14:28 +0000 Date: Mon, 6 Apr 2026 22:14:21 -0700 From: Matthew Brost To: Joel Fernandes CC: , Miguel Ojeda , "Boqun Feng" , Gary Guo , Bjorn Roy Baron , Benno Lossin , "Andreas Hindborg" , Alice Ryhl , "Trevor Gross" , Danilo Krummrich , Dave Airlie , Daniel Almeida , "Koen Koning" , , , Nikola Djukic , "Maarten Lankhorst" , Maxime Ripard , Thomas Zimmermann , David Airlie , Simona Vetter , Jonathan Corbet , Alex Deucher , Christian Koenig , Jani Nikula , "Joonas Lahtinen" , Rodrigo Vivi , Tvrtko Ursulin , Huang Rui , Matthew Auld , Lucas De Marchi , Thomas Hellstrom , Helge Deller , Alex Gaynor , Boqun Feng , John Hubbard , Alistair Popple , Timur Tabi , Edwin Peer , Alexandre Courbot , Andrea Righi , Andy Ritger , Zhi Wang , Balbir Singh , Philipp Stanner , Elle Rhumsaa , , Eliot Courtney , , , , , , Subject: Re: [PATCH v10 07/21] gpu: nova-core: mm: Add TLB flush support Message-ID: References: <20260311004008.2208806-1-joelagnelf@nvidia.com> <20260331212048.2229260-1-joelagnelf@nvidia.com> <20260331212048.2229260-8-joelagnelf@nvidia.com> <0f5605c1-32e8-4a62-b852-b1db01e42817@nvidia.com> <39a476f4-ecac-4313-a59f-e00e72d2b426@nvidia.com> Content-Type: text/plain; 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The Tlb struct provides flush > >>> functionality through BAR0 registers. > >>> > >>> The flush operation writes the page directory base address and triggers > >>> an invalidation, polling for completion with a 2 second timeout matching > >>> the Nouveau driver. > >>> > >>> Cc: Nikola Djukic > >>> Signed-off-by: Joel Fernandes > >>> --- > >>> drivers/gpu/nova-core/mm.rs | 1 + > >>> drivers/gpu/nova-core/mm/tlb.rs | 95 +++++++++++++++++++++++++++++++++ > >>> drivers/gpu/nova-core/regs.rs | 42 +++++++++++++++ > >>> 3 files changed, 138 insertions(+) > >>> create mode 100644 drivers/gpu/nova-core/mm/tlb.rs > >>> > >>> diff --git a/drivers/gpu/nova-core/mm.rs b/drivers/gpu/nova-core/mm.rs > >>> index 8f3089a5fa88..cfe9cbe11d57 100644 > >>> --- a/drivers/gpu/nova-core/mm.rs > >>> +++ b/drivers/gpu/nova-core/mm.rs > >>> @@ -5,6 +5,7 @@ > >>> #![expect(dead_code)] > >>> > >>> pub(crate) mod pramin; > >>> +pub(crate) mod tlb; > >>> > >>> use kernel::sizes::SZ_4K; > >>> > >>> diff --git a/drivers/gpu/nova-core/mm/tlb.rs b/drivers/gpu/nova-core/mm/tlb.rs > >>> new file mode 100644 > >>> index 000000000000..cd3cbcf4c739 > >>> --- /dev/null > >>> +++ b/drivers/gpu/nova-core/mm/tlb.rs > >>> @@ -0,0 +1,95 @@ > >>> +// SPDX-License-Identifier: GPL-2.0 > >>> + > >>> +//! TLB (Translation Lookaside Buffer) flush support for GPU MMU. > >>> +//! > >>> +//! After modifying page table entries, the GPU's TLB must be flushed to > >>> +//! ensure the new mappings take effect. This module provides TLB flush > >>> +//! functionality for virtual memory managers. > >>> +//! > >>> +//! # Example > >>> +//! > >>> +//! ```ignore > >>> +//! use crate::mm::tlb::Tlb; > >>> +//! > >>> +//! fn page_table_update(tlb: &Tlb, pdb_addr: VramAddress) -> Result<()> { > >>> +//! // ... modify page tables ... > >>> +//! > >>> +//! // Flush TLB to make changes visible (polls for completion). > >>> +//! tlb.flush(pdb_addr)?; > >>> +//! > >>> +//! Ok(()) > >>> +//! } > >>> +//! ``` > >>> + > >>> +use kernel::{ > >>> + devres::Devres, > >>> + io::poll::read_poll_timeout, > >>> + io::Io, > >>> + new_mutex, > >>> + prelude::*, > >>> + sync::{ > >>> + Arc, > >>> + Mutex, // > >>> + }, > >>> + time::Delta, // > >>> +}; > >>> + > >>> +use crate::{ > >>> + driver::Bar0, > >>> + mm::VramAddress, > >>> + regs, // > >>> +}; > >>> + > >>> +/// TLB manager for GPU translation buffer operations. > >>> +#[pin_data] > >>> +pub(crate) struct Tlb { > >>> + bar: Arc>, > >>> + /// TLB flush serialization lock: This lock is acquired during the > >>> + /// DMA fence signalling critical path. It must NEVER be held across any > >>> + /// reclaimable CPU memory allocations because the memory reclaim path can > >>> + /// call `dma_fence_wait()`, which would deadlock with this lock held. > >>> + #[pin] > >>> + lock: Mutex<()>, > >>> +} > >>> + > >>> +impl Tlb { > >>> + /// Create a new TLB manager. > >>> + pub(super) fn new(bar: Arc>) -> impl PinInit { > >>> + pin_init!(Self { > >>> + bar, > >>> + lock <- new_mutex!((), "tlb_flush"), > >>> + }) > >>> + } > >>> + > >>> + /// Flush the GPU TLB for a specific page directory base. > >>> + /// > >>> + /// This invalidates all TLB entries associated with the given PDB address. > >>> + /// Must be called after modifying page table entries to ensure the GPU sees > >>> + /// the updated mappings. > >>> + pub(crate) fn flush(&self, pdb_addr: VramAddress) -> Result { > >> > >> This landed on my list randomly, so I took a look. > >> > >> Wouldn’t you want to virtualize the invalidation based on your device? > >> For example, what if you need to register interface changes on future hardware? > > > > Good point, for future hardware it indeed makes sense. I will do that. > Actually, at least in the future as far as I can see, the register definitions > are the same for TLB invalidation are the same, so we are good and I will not be > making any change in this regard. > > But, thanks for raising the point and forcing me to double check! > Not my driver, but this looks like a classic “works now” change that may not hold up later, which is why I replied to something that isn’t really my business. Again, not my area, but I’ve been through this before. Generally, getting the abstractions right up front pays off. Matt > -- > Joel Fernandes >