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AHgh+Rqo4SDN3IWSzGstt4cndbWTE7GfNmTJ6bYtTKD/LZRpshRSb7/mT7DNkQ03o3wUAi7TgfCPypUaQvJUF70RaQ==@vger.kernel.org X-Gm-Message-State: AOJu0YwSOC8H9oEh/jaOIevBLdqwL9a81GGgnJrJz8zyEAjPicG3XhWi rEuYhsqf/pNV/oGfZFDMpwTt2c6qRsi/RHw0oRaOLuuueIrICHxdPMtk1egLGBA0UKe5YjurOZB g+GkoUpPUnbvrE9sVKA== X-Received: from wmix24-n2.prod.google.com ([2002:a05:600c:e558:20b0:497:ffd5:d12]) (user=aliceryhl job=prod-delivery.src-stubby-dispatcher) by 2002:a05:600c:a21b:b0:495:4e89:3f30 with SMTP id 5b1f17b1804b1-4994e7c5e49mr131672365e9.15.1786004835498; Thu, 06 Aug 2026 01:27:15 -0700 (PDT) Date: Thu, 6 Aug 2026 08:27:14 +0000 In-Reply-To: <20260805104815.104154-1-laura.nao@collabora.com> Precedence: bulk X-Mailing-List: rust-for-linux@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 References: <20260805104815.104154-1-laura.nao@collabora.com> Message-ID: Subject: Re: [PATCH v3] drm/tyr: add Job IRQ handling From: Alice Ryhl To: Laura Nao Cc: linkmauve@linkmauve.fr, a.hindborg@kernel.org, acourbot@nvidia.com, airlied@gmail.com, bjorn3_gh@protonmail.com, boqun@kernel.org, dakr@kernel.org, daniel.almeida@collabora.com, deborah.brouwer@collabora.com, dri-devel@lists.freedesktop.org, gary@garyguo.net, kernel@collabora.com, linux-kernel@vger.kernel.org, lossin@kernel.org, ojeda@kernel.org, rust-for-linux@vger.kernel.org, simona@ffwll.ch, tamird@kernel.org, tmgross@umich.edu, work@onurozkan.dev Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable On Wed, Aug 05, 2026 at 12:48:15PM +0200, Laura Nao wrote: > Hello, >=20 > On 8/4/26 14:23, Link Mauve wrote: > > Hi, > > > > On Mon, Aug 03, 2026 at 03:34:37PM +0200, Laura Nao wrote: > >> Add a threaded IRQ wrapper for Tyr interrupt sources and use it to > >> handle the firmware Job IRQ. > >> > >> The Job IRQ reports requests from the CSF firmware, including global > >> interface requests and CSG attention bits. Only the GLB bit is current= ly > >> handled, as it will be used to check firmware readiness. CSG bits > >> handling will be added at a later stage. Add a Job IRQ handler that > >> masks the interrupt in the primary IRQ handler, processes pending raw > >> status in the threaded handler, clears the handled bit, and reenables > >> the mask before returning. > >> Add a wait queue and a bool flag so the handler can signal firmware > >> readiness when the GLB bit is set. > > [=E2=80=A6] > >> diff --git a/drivers/gpu/drm/tyr/fw/irq.rs b/drivers/gpu/drm/tyr/fw/ir= q.rs > >> new file mode 100644 > >> index 000000000000..6eeb1399a7b3 > >> --- /dev/null > >> +++ b/drivers/gpu/drm/tyr/fw/irq.rs > >> @@ -0,0 +1,105 @@ > > [=E2=80=A6] > >> +/// Requests a threaded IRQ registration for the Job IRQ. > >> +/// > >> +/// # Safety > >> +/// > >> +/// Callers must not `mem::forget()` the resulting registration or ot= herwise prevent its > >> +/// [`Drop`] implementation from running. > >> +pub(crate) unsafe fn job_irq_init<'a>( > >> + pdev: &'a platform::Device, > >> + iomem: Arc>, > >> + fw_ready: Arc, > >> + job_irq_wait: Arc, > >> +) -> Result>>= , Error> + 'a> { > >> + iomem.write_reg(JOB_IRQ_MASK::zeroed().with_glb(true)); > >> + let job_irq =3D JobIrq { > >> + iomem: iomem.clone(), > >> + fw_ready, > >> + job_irq_wait, > >> + }; > >> + // SAFETY: The caller guarantees the resulting registration will = not be leaked. > >> + unsafe { TyrIrq::request(pdev, c_str!("job"), job_irq) } > > > > Nowadays we use the shorter c"job" way of creating a &CStr, and I think > > the macro will even generate warnings in some configurations (perhaps > > CLIPPY=3D1?). > > >=20 > Got it, I didn't get the warning with CLIPPY=3D1, I'll double check my > configuration.=20 There's not any warning for using it, because macros still need it sometimes. Alice