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[46.150.62.216]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-45491da03a7sm20304842f8f.33.2026.05.10.12.11.51 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 10 May 2026 12:11:51 -0700 (PDT) From: Jernej =?UTF-8?B?xaBrcmFiZWM=?= To: sashiko@lists.linux.dev Cc: devicetree@vger.kernel.org, krzk+dt@kernel.org, robh@kernel.org, conor+dt@kernel.org Subject: Re: [PATCH v2 1/8] clk: sunxi-ng: de2: Fix Display Engine 3.3 definitions Date: Sun, 10 May 2026 21:11:50 +0200 Message-ID: <2WzKBHuPSreDENZ3eIUvdg@gmail.com> In-Reply-To: <20260509194402.EB552C2BCB2@smtp.kernel.org> References: <20260509190015.79086-2-jernej.skrabec@siol.net> <20260509194402.EB552C2BCB2@smtp.kernel.org> Precedence: bulk X-Mailing-List: sashiko@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8" Dne sobota, 9. maj 2026 ob 21:44:02 Srednjeevropski poletni =C4=8Das je sas= hiko-bot@kernel.org napisal(a): > Thank you for your contribution! Sashiko AI review found 1 potential issu= e(s) to consider: > - [High] The new DE33 clock definitions omit the bus clocks for MIXER1 an= d WB, leaving their bus interfaces unclocked and breaking hardware support. > -- >=20 > commit 7e5df4616faf2d32c9447b44291572215aac8a17 > Author: Jernej Skrabec >=20 > clk: sunxi-ng: de2: Fix Display Engine 3.3 definitions >=20 > This commit fixes the Display Engine 3.3 resets and clocks to match > the vendor driver, as the positions of clocks and resets changed in > version 3.3. >=20 > > diff --git a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c b/drivers/clk/sunxi-n= g/ccu-sun8i-de2.c > > index a6cd0f988859d..6ec6c0dc4c261 100644 > > --- a/drivers/clk/sunxi-ng/ccu-sun8i-de2.c > > +++ b/drivers/clk/sunxi-ng/ccu-sun8i-de2.c >=20 > [ ... ] >=20 > > @@ -54,6 +61,9 @@ static SUNXI_CCU_M(wb_div_a83_clk, "wb-div", "pll-de"= , 0x0c, 8, 4, > > static SUNXI_CCU_M(rot_div_a83_clk, "rot-div", "pll-de", 0x0c, 0x0c, 4, > > CLK_SET_RATE_PARENT); > > =20 > > +static SUNXI_CCU_GATE(bus_mixer0_h616_clk, "bus-mixer0", "bus-de", > > + 0x08, BIT(0), 0); > > + >=20 > Will this omission cause a regression for mixer1 and wb? No, I should explain in commit message that there is only one bus clock, shared among mixer0, mixer1 and wb. CLK_BUS_MIXER0 is used for all cores. >=20 > It looks like the bus clocks for mixer1 (BIT(1)) and wb (BIT(4)) at regis= ter > offset 0x08 are missing here. >=20 > Since RST_MIXER1 was previously mapped to 0x08 BIT(1), the DRM driver > deasserting that reset was inadvertently enabling the DE33 bus clock for > mixer1. >=20 > Now that RST_MIXER1 is correctly moved to 0x00, will accessing the > unclocked MIXER1 or WB hardware blocks cause a hard system hang due to MM= IO > access failures? There are no such issues, as hardware testing showed. Old code worked by lu= ck. Best regards, Jernej >=20 > [ ... ] >=20 > > @@ -147,6 +163,17 @@ static struct clk_hw_onecell_data sun50i_a64_de2_h= w_clks =3D { > > .num =3D CLK_NUMBER_WITH_ROT, > > }; > > =20 > > +static struct clk_hw_onecell_data sun50i_h616_de33_hw_clks =3D { > > + .hws =3D { > > + [CLK_MIXER0] =3D &mixer0_h616_clk.common.hw, > > + [CLK_MIXER1] =3D &mixer1_h616_clk.common.hw, > > + [CLK_WB] =3D &wb_h616_clk.common.hw, > > + > > + [CLK_BUS_MIXER0] =3D &bus_mixer0_h616_clk.common.hw, >=20 > Similarly, should the bus clocks for mixer1 and wb be populated in this > array so the DRM driver can properly request and enable them? >=20 > > + }, > > + .num =3D CLK_NUMBER_WITHOUT_ROT, > > +}; >=20 >=20