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Mon, 10 Feb 2025 07:01:12 -0800 (PST) Message-ID: <03ff407fe68e46df4844e5dd244e7c609331af71.camel@gmail.com> Subject: Re: [PATCH 03/10] arm64: dts: sophgo: Add initial SG2000 SoC device tree From: Alexander Sverdlin To: Krzysztof Kozlowski , soc@lists.linux.dev Cc: Chen Wang , Inochi Amaoto , linux-riscv@lists.infradead.org, devicetree@vger.kernel.org, Haylen Chu , linux-arm-kernel@lists.infradead.org, Arnd Bergmann , Rob Herring , Krzysztof Kozlowski , Conor Dooley Date: Mon, 10 Feb 2025 16:01:10 +0100 In-Reply-To: <0d5484d1-be83-4f38-befd-94d458b3aaa8@kernel.org> References: <20250209220646.1090868-1-alexander.sverdlin@gmail.com> <20250209220646.1090868-4-alexander.sverdlin@gmail.com> <0d5484d1-be83-4f38-befd-94d458b3aaa8@kernel.org> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.54.2 Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Krzysztof! On Mon, 2025-02-10 at 09:45 +0100, Krzysztof Kozlowski wrote: > On 09/02/2025 23:06, Alexander Sverdlin wrote: > > Add initial device tree for the SG2000 SoC by SOPHGO (from ARM64 PoV). > >=20 > > Signed-off-by: Alexander Sverdlin > > --- > > =C2=A0 arch/arm64/boot/dts/sophgo/sg2000.dtsi | 79 ++++++++++++++++++++= ++++++ > > =C2=A0 1 file changed, 79 insertions(+) > > =C2=A0 create mode 100644 arch/arm64/boot/dts/sophgo/sg2000.dtsi > >=20 > > diff --git a/arch/arm64/boot/dts/sophgo/sg2000.dtsi b/arch/arm64/boot/d= ts/sophgo/sg2000.dtsi > > new file mode 100644 > > index 000000000000..4e520486cbe5 > > --- /dev/null > > +++ b/arch/arm64/boot/dts/sophgo/sg2000.dtsi > > @@ -0,0 +1,79 @@ > > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > > + > > +#define SOC_PERIPHERAL_IRQ(nr) GIC_SPI (nr) > > + > > +#include > > +#include > > +#include > > + > > +/ { [...] > > + gic: interrupt-controller@1f01000 { >=20 > MMIO nodes are always in the soc. I think I've looked a wrong example (or a counter-example)... $ grep -R -P '^\t\tcompatible =3D "arm,cortex-a15-gic";' * arm/boot/dts/intel/axm/axm55xx.dtsi: compatible =3D "arm,cortex-a15-gic"; arm/boot/dts/ti/omap/dra7.dtsi: compatible =3D "arm,cortex-a15-gic"; arm/boot/dts/ti/omap/omap5.dtsi: compatible =3D "arm,cortex-a15-gic"; arm/boot/dts/nvidia/tegra124.dtsi: compatible =3D "arm,cortex-a15-gic"; arm/boot/dts/nvidia/tegra114.dtsi: compatible =3D "arm,cortex-a15-gic"; arm64/boot/dts/nvidia/tegra132.dtsi: compatible =3D "arm,cortex-a15-gic"; arm64/boot/dts/freescale/s32v234.dtsi: compatible =3D "arm,cortex-a15-gic"= ; arm64/boot/dts/apm/apm-storm.dtsi: compatible =3D "arm,cortex-a15-gic"; arm64/boot/dts/apm/apm-shadowcat.dtsi: compatible =3D "arm,cortex-a15-gic"= ; But thanks for clarification! > > + compatible =3D "arm,cortex-a15-gic"; > > + interrupt-controller; > > + #interrupt-cells =3D <3>; > > + reg =3D <0x01f01000 0x1000>, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x01f02000 0x2000>; > > + }; > > + > > + soc { >=20 > Override by phandle/label instead of duplicating. >=20 > > + ranges; > > + > > + pinctrl: pinctrl@3001000 { > > + compatible =3D "sophgo,sg2000-pinctrl"; > > + reg =3D <0x03001000 0x1000>, > > + =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 <0x05027000 0x1000>; > > + reg-names =3D "sys", "rtc"; > > + }; > > + }; > > +}; > > + > > + > > +&clk { > > + compatible =3D "sophgo,sg2000-clk"; >=20 >=20 > That's discouraged practice. If you need to define compatible, it means > the block is not shared between designs and must not be in common DTSI. That doesn't come from my series, that's how original cv18xx.dtsi has been designed. Same question as before: do I need to rework it if I will not be = able to test the changes (I don't even posess the relevant HW). But if not, I have to adapt the same pattern into the new sg2000.dtsi. --=20 Alexander Sverdlin.