From: patchwork-bot+linux-soc@kernel.org
To: None <gordon.ge@bst.ai>
Cc: soc@kernel.org
Subject: Re: [PATCH] arm64: dts: bst: enable eMMC controller in C1200
Date: Fri, 12 Jun 2026 07:30:05 +0000 [thread overview]
Message-ID: <178124940514.526649.8766889787305579928.git-patchwork-notify@kernel.org> (raw)
In-Reply-To: <178123037729.455092.8454252669856079676@bst.ai>
Hello:
This patch was applied to soc/soc.git (for-next)
by Gordon Ge <gordon.ge@bst.ai>:
On Fri, 12 Jun 2026 08:40:23 +0800 you wrote:
> Add mmc0 node for the DWCMSHC SDHCI controller with basic configuration
> (disabled by default) and fixed clock definition in bstc1200.dtsi.
>
> Enable mmc0 with board-specific configuration including 8-bit bus
> width and reserved SRAM bounce buffer on the CDCU1.0 ADAS 4C2G board.
>
> The bounce buffer in reserved SRAM addresses hardware constraints
> where the eMMC controller cannot access main system memory through
> SMMU due to a hardware bug, and all DRAM is located outside the
> 4GB boundary.
>
> [...]
Here is the summary with links:
- arm64: dts: bst: enable eMMC controller in C1200
https://git.kernel.org/soc/soc/c/6191a61ec9d9
You are awesome, thank you!
--
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prev parent reply other threads:[~2026-06-12 7:30 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-12 0:40 [PATCH] arm64: dts: bst: enable eMMC controller in C1200 gordon.ge
2026-06-12 0:42 ` [PATCH] arm64: defconfig: enable BST SDHCI controller gordon.ge
2026-06-12 7:30 ` patchwork-bot+linux-soc
2026-06-12 7:30 ` patchwork-bot+linux-soc [this message]
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