From: "Rob Herring (Arm)" <robh@kernel.org>
To: soc@kernel.org, Robert Richter <rric@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org
Subject: [PATCH] arm64: dts: cavium: thunder2: Add missing PL011 "uartclk"
Date: Mon, 9 Jun 2025 16:57:06 -0500 [thread overview]
Message-ID: <20250609215706.3009692-2-robh@kernel.org> (raw)
The PL011 IP has 2 clock inputs for UART core/baud and APB bus. The
Thunder2 SoC is missing the core "uartclk". In this case, the Linux
driver uses single clock for both clock inputs. Let's assume that's how
the h/w is wired and make the DT reflect that.
Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
---
Arnd, Please apply directly.
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
index 6dfe78a7d4ab..966fb57280f3 100644
--- a/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
+++ b/arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
@@ -136,8 +136,8 @@ uart0: serial@402020000 {
reg = <0x04 0x02020000 0x0 0x1000>;
interrupt-parent = <&gic>;
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&clk125mhz>;
- clock-names = "apb_pclk";
+ clocks = <&clk125mhz>, <&clk125mhz>;
+ clock-names = "uartclk", "apb_pclk";
};
};
--
2.47.2
next reply other threads:[~2025-06-09 21:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-09 21:57 Rob Herring (Arm) [this message]
2025-07-03 16:00 ` [PATCH] arm64: dts: cavium: thunder2: Add missing PL011 "uartclk" patchwork-bot+linux-soc
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