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[60.250.196.139]) by smtp.gmail.com with ESMTPSA id d9443c01a7336-2ccc9d3d952sm24010315ad.61.2026.07.08.01.25.15 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 08 Jul 2026 01:25:18 -0700 (PDT) From: Zi-Yu Chen To: arnd@arndb.de, olof@lixom.net Cc: soc@lists.linux.dev, ychuang3@nuvoton.com, schung@nuvoton.com, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Zi-Yu Chen Subject: [PATCH v2 RESEND] arm64: dts: nuvoton: ma35d1: add CAN nodes Date: Wed, 8 Jul 2026 16:24:57 +0800 Message-Id: <20260708082457.460710-1-zychennvt@gmail.com> X-Mailer: git-send-email 2.34.1 Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Add controller nodes for the four Bosch M_CAN blocks found on the Nuvoton MA35D1 SoC. Additionally, configure pinctrl and enable CAN1 and CAN3 on the MA35D1 SOM board. Also, update the APLL frequency to 200MHz to ensure the CAN controllers receive the required input clock for 50MHz operation. Signed-off-by: Zi-Yu Chen --- Resend note: - resend with the complete Cc list; no patch changes .../boot/dts/nuvoton/ma35d1-som-256m.dts | 32 +++++++++++- arch/arm64/boot/dts/nuvoton/ma35d1.dtsi | 52 +++++++++++++++++++ 2 files changed, 83 insertions(+), 1 deletion(-) diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts index f6f20a17e501..fb23b0573bdc 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts +++ b/arch/arm64/boot/dts/nuvoton/ma35d1-som-256m.dts @@ -37,6 +37,22 @@ clk_hxt: clock-hxt { }; }; +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can1>; + assigned-clocks = <&clk CAN1_DIV>; + assigned-clock-rates = <50000000>; + status = "okay"; +}; + +&can3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_can3>; + assigned-clocks = <&clk CAN3_DIV>; + assigned-clock-rates = <50000000>; + status = "okay"; +}; + &clk { assigned-clocks = <&clk CAPLL>, <&clk DDRPLL>, @@ -45,7 +61,7 @@ &clk { <&clk VPLL>; assigned-clock-rates = <800000000>, <266000000>, - <180000000>, + <200000000>, <500000000>, <102000000>; nuvoton,pll-mode = "integer", @@ -56,6 +72,20 @@ &clk { }; &pinctrl { + can-grp { + pinctrl_can1: can1-pins { + nuvoton,pins = <11 14 4>, + <11 15 4>; + bias-disable; + }; + + pinctrl_can3: can3-pins { + nuvoton,pins = <11 10 3>, + <11 11 3>; + bias-disable; + }; + }; + uart-grp { pinctrl_uart0: uart0-pins { nuvoton,pins = <4 14 1>, diff --git a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi index e51b98f5bdce..494724a25f3b 100644 --- a/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi +++ b/arch/arm64/boot/dts/nuvoton/ma35d1.dtsi @@ -244,6 +244,58 @@ gpion: gpio@340 { }; }; + can0: can@403c0000 { + compatible = "bosch,m_can"; + reg = <0x0 0x403c0000 0x0 0x200>, <0x0 0x403c0200 0x0 0x2000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clk HCLK3>, <&clk CAN0_GATE>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 4 4 32 32 32 8 8>; + status = "disabled"; + }; + + can1: can@403d0000 { + compatible = "bosch,m_can"; + reg = <0x0 0x403d0000 0x0 0x200>, <0x0 0x403d0200 0x0 0x2000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clk HCLK3>, <&clk CAN1_GATE>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 4 4 32 32 32 8 8>; + status = "disabled"; + }; + + can2: can@403e0000 { + compatible = "bosch,m_can"; + reg = <0x0 0x403e0000 0x0 0x200>, <0x0 0x403e0200 0x0 0x2000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clk HCLK3>, <&clk CAN2_GATE>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 4 4 32 32 32 8 8>; + status = "disabled"; + }; + + can3: can@403f0000 { + compatible = "bosch,m_can"; + reg = <0x0 0x403f0000 0x0 0x200>, <0x0 0x403f0200 0x0 0x2000>; + reg-names = "m_can", "message_ram"; + interrupts = , + ; + interrupt-names = "int0", "int1"; + clocks = <&clk HCLK3>, <&clk CAN3_GATE>; + clock-names = "hclk", "cclk"; + bosch,mram-cfg = <0x0 4 4 32 32 32 8 8>; + status = "disabled"; + }; + uart0: serial@40700000 { compatible = "nuvoton,ma35d1-uart"; reg = <0x0 0x40700000 0x0 0x100>; -- 2.34.1