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Thu, 12 Oct 2023 05:24:41 -0700 (PDT) Received: from [192.168.1.20] ([178.197.219.100]) by smtp.gmail.com with ESMTPSA id l14-20020a5d480e000000b0031c5e9c2ed7sm18366425wrq.92.2023.10.12.05.24.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 12 Oct 2023 05:24:40 -0700 (PDT) Message-ID: <28bee37b-1d6d-433e-810f-da847635fcaf@linaro.org> Date: Thu, 12 Oct 2023 14:24:35 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v3 10/20] clk: samsung: clk-gs101: Add cmu_top registers, plls, mux and gates To: Peter Griffin , Sam Protsenko List-Id: Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, cw00.choi@samsung.com, tudor.ambarus@linaro.org, andre.draszik@linaro.org, saravanak@google.com, willmcvicker@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org References: <20231011184823.443959-1-peter.griffin@linaro.org> <20231011184823.443959-11-peter.griffin@linaro.org> Content-Language: en-US From: Krzysztof Kozlowski Autocrypt: addr=krzysztof.kozlowski@linaro.org; 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charset=UTF-8 Content-Transfer-Encoding: 8bit On 12/10/2023 14:06, Peter Griffin wrote: > Hi Sam, > > Thanks for the review. > > On Thu, 12 Oct 2023 at 01:07, Sam Protsenko wrote: >> >> On Wed, Oct 11, 2023 at 1:49 PM Peter Griffin wrote: >>> >>> CMU_TOP is the top level clock management unit which contains PLLs, muxes >>> and gates that feed the other clock management units. >>> >>> Signed-off-by: Peter Griffin >>> --- >>> drivers/clk/samsung/Kconfig | 9 + >>> drivers/clk/samsung/Makefile | 2 + >>> drivers/clk/samsung/clk-gs101.c | 1551 +++++++++++++++++++++++++++++++ >>> 3 files changed, 1562 insertions(+) >>> create mode 100644 drivers/clk/samsung/clk-gs101.c >>> >>> diff --git a/drivers/clk/samsung/Kconfig b/drivers/clk/samsung/Kconfig >>> index 76a494e95027..14362ec9c543 100644 >>> --- a/drivers/clk/samsung/Kconfig >>> +++ b/drivers/clk/samsung/Kconfig >>> @@ -12,6 +12,7 @@ config COMMON_CLK_SAMSUNG >>> select EXYNOS_5410_COMMON_CLK if ARM && SOC_EXYNOS5410 >>> select EXYNOS_5420_COMMON_CLK if ARM && SOC_EXYNOS5420 >>> select EXYNOS_ARM64_COMMON_CLK if ARM64 && ARCH_EXYNOS >>> + select GOOGLE_GS101_COMMON_CLK if ARM64 && ARCH_GOOGLE_TENSOR >>> select TESLA_FSD_COMMON_CLK if ARM64 && ARCH_TESLA_FSD >>> >>> config S3C64XX_COMMON_CLK >>> @@ -95,6 +96,14 @@ config EXYNOS_CLKOUT >>> status of the certains clocks from SoC, but it could also be tied to >>> other devices as an input clock. >>> >>> +config GOOGLE_GS101_COMMON_CLK >>> + bool "Google gs101 clock controller support" if COMPILE_TEST >>> + depends on COMMON_CLK_SAMSUNG >>> + depends on EXYNOS_ARM64_COMMON_CLK >>> + help >>> + Support for the clock controller present on the Google gs101 SoC. >>> + Choose Y here only if you build for this SoC. >>> + >> >> Why is that new option needed? From the look of it, it could be just a >> part of EXYNOS_ARM64_COMMON_CLK. Like clk-exynos850 or >> clk-exynosautov9. Is there any particular feature that makes it SoC >> special? > > No, it could also be added to EXYNOS_ARM64_COMMON_CLK. I was following > the example set by TESLA_FSD which is another custom Exynos based chipset > that added its own config option. > > Krzysztof do you have any preference on this? Usually there is only one image for several boards so long time ago we stopped adding per-SoC Kconfig entries. This has its own ARCH_xxx, just like Tesla, thus having separate Kconfig for all Google Tensor clock drivers makes sense. Maybe it should be just called a bit differently, e.g. GOOGLE_TENSOR_COMMON_CLK Best regards, Krzysztof