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Thu, 29 Jan 2026 11:39:53 -0800 (PST) Received: from grey.localnet ([197.250.227.106]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-435e131cefdsm16504443f8f.23.2026.01.29.11.39.49 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Jan 2026 11:39:52 -0800 (PST) From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= To: linux-arm-kernel@lists.infradead.org, Arnd Bergmann Cc: soc@lists.linux.dev, Jun Nie Subject: Re: [RFC PATCH v2 0/7] Add support for ZTE zx297520v3 Date: Thu, 29 Jan 2026 22:38:51 +0300 Message-ID: <2936803.ElGaqSPkdT@grey> In-Reply-To: References: <20260128203455.38569-1-stefandoesinger@gmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: multipart/signed; boundary="nextPart5583984.GXAFRqVoOG"; micalg="pgp-sha256"; protocol="application/pgp-signature" --nextPart5583984.GXAFRqVoOG Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset="utf-8"; protected-headers="v1" From: Stefan =?UTF-8?B?RMO2c2luZ2Vy?= Cc: soc@lists.linux.dev, Jun Nie Subject: Re: [RFC PATCH v2 0/7] Add support for ZTE zx297520v3 Date: Thu, 29 Jan 2026 22:38:51 +0300 Message-ID: <2936803.ElGaqSPkdT@grey> In-Reply-To: MIME-Version: 1.0 Am Donnerstag, 29. Januar 2026, 01:00:08 Ostafrikanische Zeit schrieb Arnd= =20 Bergmann: > On Wed, Jan 28, 2026, at 21:34, Stefan D=C3=B6singer wrote: > I assume that you were in EL3 when you tried to write to NSACR? > From EL2/EL1 it would still appear the same as not-implemented > even if it is there but disabled in EL3. Yes, and I just double checked, it does read 0 in all cases. Here's what I = did=20 =2D abusing the head.S error handling code a bit for printing: cps #MON_MODE mrc p15, 0, r9, c1, c1, 2 b __error_p @ abuse for print Error: unrecognized/unsupported processor variant (0x00000000). cps #MON_MODE ldr r1, =3D0x63fff mcr p15, 0, r1, c1, c1, 2 mrc p15, 0, r9, c1, c1, 2 b __error_p Error: unrecognized/unsupported processor variant (0x00000000). And just to make sure I didn't get __error_p wrong: cps #MON_MODE ldr r9, =3D0xdeadbeef b __error_p Error: unrecognized/unsupported processor variant (0xdeadbeef). I am certain switching to EL3 is working here because I am using it in the= =20 same way to set up ICC_SRE_EL*. (And yes, I know this code doesn't belong i= n=20 this place. It's just more comfortable for my development tree for now) > I've never seen a Cortex-A53 without FPU and NEON, but since this > is optional, it was a matter of time before we got one ;-) The ZTE 3.4 kernel code suggests that there is/was a zx297520v2 that was=20 Cortex A9 based, and then ZTE replaced the Cortex-A9 with a Cortex-A53 and= =20 left the rest of the system unchanged. A later version of this SoC, zx298501 switched to 64 bit, including kernel = +=20 userland. But I don't have any hardware based on either of them. > Support for 64-bit cores is actually quite rudimentary in 32-bit > more, as we are missing a lot of the errata workarounds and ARMv8 > specific features in the kernel. If you can figure out how to > use 64-bit kernel mode, that would be ideal. One of my co-hackers is giving it another try. Pairing a 64 bit kernel with= 32=20 bit userspace seems reasonable. Of course the other question is what quirks= =20 are hiding in the hardware when we run them in a mode the vendor never test= ed. > > 6) The old removed zx29 code used "zte," as the vendor for the > > compatibles. Sanechips is a subsidiary of ZTE that designed these chips. > > Are there any preferences for either "zte," or "sanechips,"? >=20 > I would stay with the previously used one Check Cheers, Stefan --nextPart5583984.GXAFRqVoOG Content-Type: application/pgp-signature; name="signature.asc" Content-Description: This is a digitally signed message part. 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