From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 53CAFC4332F for ; Wed, 4 Jan 2023 09:51:06 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 246C8C433D2; Wed, 4 Jan 2023 09:51:06 +0000 (UTC) Received: from imap4.hz.codethink.co.uk (imap4.hz.codethink.co.uk [188.40.203.114]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 30D3FC433EF; Wed, 4 Jan 2023 09:51:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 30D3FC433EF Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=codethink.co.uk Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=codethink.co.uk Received: from cpc152649-stkp13-2-0-cust121.10-2.cable.virginm.net ([86.15.83.122] helo=[192.168.0.17]) by imap4.hz.codethink.co.uk with esmtpsa (Exim 4.94.2 #2 (Debian)) id 1pD0QG-00G85N-8X; Wed, 04 Jan 2023 09:51:00 +0000 Message-ID: <49bd7b4a-b0e1-3213-8aed-9f39604f3935@codethink.co.uk> Date: Wed, 4 Jan 2023 09:50:58 +0000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [RFC v5.1 6/9] cache,soc: Move SiFive CCache driver & create drivers/cache Content-Language: en-GB To: Conor Dooley , arnd@arndb.de, palmer@dabbelt.com, prabhakar.csengg@gmail.com List-Id: Cc: Conor Dooley , ajones@ventanamicro.com, aou@eecs.berkeley.edu, apatel@ventanamicro.com, atishp@rivosinc.com, biju.das.jz@bp.renesas.com, devicetree@vger.kernel.org, geert@linux-m68k.org, guoren@kernel.org, hch@infradead.org, heiko@sntech.de, jszhang@kernel.org, krzysztof.kozlowski+dt@linaro.org, linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org, linux-riscv@lists.infradead.org, magnus.damm@gmail.com, nathan@kernel.org, paul.walmsley@sifive.com, philipp.tomsich@vrull.eu, prabhakar.mahadev-lad.rj@bp.renesas.com, robh+dt@kernel.org, samuel@sholland.org, soc@kernel.org References: <20230103210400.3500626-7-conor@kernel.org> From: Ben Dooks Organization: Codethink Limited. In-Reply-To: <20230103210400.3500626-7-conor@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 03/01/2023 21:03, Conor Dooley wrote: > From: Conor Dooley > > The Zicbo* set of extensions for cache maintenance arrived too late & > several SoCs exist without them that require non-coherent DMA. > As things stand, the StarFive JH7100, Microchip PolarFire SoC & Renesas > RZ/Five all require cache maintenance and lack instructions for this > purpose. > Create a subsystem for cache drivers so that vendor specific behaviour > can be isolated from arch code, but keep the interfaces etc consistent. > Move the existing SiFive CCache driver to create drivers/cache. > > Signed-off-by: Conor Dooley > --- > MAINTAINERS | 15 ++++++++------- > drivers/Kconfig | 2 ++ > drivers/Makefile | 2 ++ > drivers/{soc/sifive => cache}/Kconfig | 8 +++++++- > drivers/{soc/sifive => cache}/Makefile | 0 > drivers/{soc/sifive => cache}/sifive_ccache.c | 2 +- > drivers/edac/sifive_edac.c | 2 +- > drivers/soc/Kconfig | 1 - > drivers/soc/Makefile | 1 - > include/{soc/sifive => cache}/sifive_ccache.h | 0 > 10 files changed, 21 insertions(+), 12 deletions(-) > rename drivers/{soc/sifive => cache}/Kconfig (56%) > rename drivers/{soc/sifive => cache}/Makefile (100%) > rename drivers/{soc/sifive => cache}/sifive_ccache.c (99%) > rename include/{soc/sifive => cache}/sifive_ccache.h (100%) > > diff --git a/MAINTAINERS b/MAINTAINERS > index f61eb221415b..4437e96a657b 100644 > --- a/MAINTAINERS > +++ b/MAINTAINERS > @@ -19054,13 +19054,6 @@ S: Maintained > F: Documentation/devicetree/bindings/dma/sifive,fu540-c000-pdma.yaml > F: drivers/dma/sf-pdma/ > > -SIFIVE SOC DRIVERS > -M: Conor Dooley > -L: linux-riscv@lists.infradead.org > -S: Maintained > -T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ > -F: drivers/soc/sifive/ > - > SILEAD TOUCHSCREEN DRIVER > M: Hans de Goede > L: linux-input@vger.kernel.org > @@ -19873,6 +19866,14 @@ S: Supported > T: git git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/staging.git > F: drivers/staging/ > > +STANDALONE CACHE CONTROLLER DRIVERS > +M: Conor Dooley > +L: linux-riscv@lists.infradead.org > +S: Maintained > +T: git https://git.kernel.org/pub/scm/linux/kernel/git/conor/linux.git/ > +F: drivers/cache > +F: include/cache I thought the riscv list was subscribers only? Maybe if we do the suggestion of other cache drivers here we should either use the main kernel one or find some arch non-specific list. > + > STARFIRE/DURALAN NETWORK DRIVER > M: Ion Badulescu > S: Odd Fixes > diff --git a/drivers/Kconfig b/drivers/Kconfig > index 968bd0a6fd78..e592ba5276ae 100644 > --- a/drivers/Kconfig > +++ b/drivers/Kconfig > @@ -241,4 +241,6 @@ source "drivers/peci/Kconfig" > > source "drivers/hte/Kconfig" > > +source "drivers/cache/Kconfig" > + > endmenu > diff --git a/drivers/Makefile b/drivers/Makefile > index bdf1c66141c9..6ff60cf21823 100644 > --- a/drivers/Makefile > +++ b/drivers/Makefile > @@ -38,6 +38,8 @@ obj-y += clk/ > # really early. > obj-$(CONFIG_DMADEVICES) += dma/ > > +obj-y += cache/ > + > # SOC specific infrastructure drivers. > obj-y += soc/ > > diff --git a/drivers/soc/sifive/Kconfig b/drivers/cache/Kconfig > similarity index 56% > rename from drivers/soc/sifive/Kconfig > rename to drivers/cache/Kconfig > index ed4c571f8771..bc852f005c10 100644 > --- a/drivers/soc/sifive/Kconfig > +++ b/drivers/cache/Kconfig > @@ -1,9 +1,15 @@ > # SPDX-License-Identifier: GPL-2.0 > > -if SOC_SIFIVE > +menuconfig CACHE_CONTROLLER > + bool "Cache controller driver support" > + default y if RISCV > + > +if CACHE_CONTROLLER > > config SIFIVE_CCACHE > bool "Sifive Composable Cache controller" > + depends on RISCV > + default y > help > Support for the composable cache controller on SiFive platforms. > Maybe we should find and move the ARM PL cache controllers and have them here too? -- Ben Dooks http://www.codethink.co.uk/ Senior Engineer Codethink - Providing Genius https://www.codethink.co.uk/privacy.html