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Tue, 29 Apr 2025 12:10:58 -0700 (PDT) Message-ID: <70bc994b1e79c8d0d4c0010611c2e65042cff74f.camel@gmail.com> Subject: Re: [PATCH v5 1/7] riscv: dts: sophgo: cv18xx: Move RiscV-specific part into SoCs' .dtsi files From: Alexander Sverdlin To: Inochi Amaoto , sophgo@lists.linux.dev, soc@lists.linux.dev Cc: Chen Wang , Jisheng Zhang , Haylen Chu , Chao Wei , devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-arm-kernel@lists.infradead.org Date: Tue, 29 Apr 2025 21:10:57 +0200 In-Reply-To: <6wlgfvc3rkhv4s3ou67fjl6j4a26vocqck5727cg6muxlz2erj@kivndcjcqc7m> References: <20250316185640.3750873-1-alexander.sverdlin@gmail.com> <20250316185640.3750873-2-alexander.sverdlin@gmail.com> <6wlgfvc3rkhv4s3ou67fjl6j4a26vocqck5727cg6muxlz2erj@kivndcjcqc7m> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.56.0 Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Hi Inochi, On Tue, 2025-04-29 at 06:35 +0800, Inochi Amaoto wrote: > > Make the peripheral device tree re-usable on ARM64 platform by moving C= PU > > core and interrupt controllers' parts into new cv18xx-cpu.dtsi and > > cv18xx-intc.dtsi. > >=20 > > Add SOC_PERIPHERAL_IRQ() macro which explicitly maps peripheral nuberin= g > > into "plic" interrupt-controller numbering. > >=20 > > Signed-off-by: Alexander Sverdlin > > --- > > Changelog: > > v5: > > v4: > > - cleanups dropped > > - cv18xx-cpu-intc.dtsi instead of cv18xx-cpu.dtsi+cv18xx-intc.dtsi > > v3: > > - &cpus node has been moved into cv18xx-cpu.dtsi, &plic and &clint node= s > > were moved into cv18xx-intc.dtsi to reduce code duplication; > > v2: > > - instead of carving out peripherals' part, carve out ARCH-specifics (C= PU > > core, interrupt controllers) and spread them among 3 SoC .dtsi files wh= ich > > included cv18xx.dtsi; > > - define a label for the "soc" node and use it in the newly introduced = DTs; > >=20 > > =C2=A0 arch/riscv/boot/dts/sophgo/cv1800b.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 |=C2=A0 5 + > > =C2=A0 arch/riscv/boot/dts/sophgo/cv1812h.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0 |=C2=A0 5 + > > =C2=A0 arch/riscv/boot/dts/sophgo/cv181x.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 |=C2=A0 2 +- > > =C2=A0 .../boot/dts/sophgo/cv18xx-cpu-intc.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0 | 54 +++++++++++ > > =C2=A0 arch/riscv/boot/dts/sophgo/cv18xx.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 | 91 +++++-------------- > > =C2=A0 arch/riscv/boot/dts/sophgo/sg2002.dtsi=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0 |=C2=A0 5 + > > =C2=A0 6 files changed, 93 insertions(+), 69 deletions(-) > > =C2=A0 create mode 100644 arch/riscv/boot/dts/sophgo/cv18xx-cpu-intc.dt= si > >=20 >=20 > It is a hard time for now to do some change across the cv18xx=20 > series, and it has become a mess. Due to the fact, I think it > is time to do some work like split some device (clk, pinctrl, > plic, intc) from cv18xx.dtsi to avoid override, and make room > for arm64 device. >=20 > Since this change contains some change similar to this patch.=20 > Would you mind me to take content of this patch, and add you > as the a co-author? thanks for looking into this! Either way is good for me! --=20 Alexander Sverdlin.