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[146.115.144.188]) by smtp.gmail.com with ESMTPSA id n15sm354561qkp.102.2021.11.02.16.38.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Nov 2021 16:38:04 -0700 (PDT) Message-ID: <9d480d93-c350-f219-e069-d12e16dabb13@gmail.com> Date: Tue, 2 Nov 2021 19:38:02 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.1 Subject: Re: [PATCH v2 07/13] clk: imx: Add initial support for i.MXRT clock driver Content-Language: en-US To: Fabio Estevam List-Id: Cc: NXP Linux Team , Michael Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Sascha Hauer , Ulf Hansson , Dong Aisheng , Stefan Agner , Linus Walleij , Greg Kroah-Hartman , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King - ARM Linux , Abel Vesa , Adrian Hunter , Jiri Slaby , Giulio Benetti , Nobuhiro Iwamatsu , linux-clk , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-kernel , linux-mmc , "open list:GPIO SUBSYSTEM" , linux-serial@vger.kernel.org References: <20211102225701.98944-1-Mr.Bossman075@gmail.com> <20211102225701.98944-8-Mr.Bossman075@gmail.com> From: Jesse Taube In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit On 11/2/21 19:34, Fabio Estevam wrote: > On Tue, Nov 2, 2021 at 7:57 PM Jesse Taube wrote: > >> +#include "clk.h" This is necessary for the indices. >> +#define ANATOP_BASE_ADDR 0x400d8000 OOPs my bad will fix. > > This is now unused. Please remove it. > >> + clk[IMXRT1050_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2); >> + clk[IMXRT1050_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); >> + clk[IMXRT1050_CLK_LPUART1] = imx_clk_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); >> + clk[IMXRT1050_CLK_LCDIF_APB] = imx_clk_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10); >> + clk[IMXRT1050_CLK_DMA] = imx_clk_gate("dma", "ipg", ccm_base + 0x7C, 6); >> + clk[IMXRT1050_CLK_DMA_MUX] = imx_clk_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); > > The imx clock drivers have been converted to the clk_hw API. > Oh will do, didn't know this. > For a reference, please check: > f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API") > > The same conversion could be done here. > >> + imx_check_clocks(clk, ARRAY_SIZE(clk)); >> + clk_data.clks = clk; >> + clk_data.clk_num = ARRAY_SIZE(clk); >> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL1_ARM]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL2_SYS]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL3_USB_OTG]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL3_PFD1_664_62M]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL2_PFD2_396M]); > > If these clocks are essential for the SoC to work, then you could pass > the CLK_IS_CRITICAL flag instead of calling clk_prepare_enable() > I'll look into that Thx From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id C839BC433FE for ; Tue, 2 Nov 2021 23:38:06 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id AAE4760FC2 for ; Tue, 2 Nov 2021 23:38:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229747AbhKBXkl (ORCPT ); Tue, 2 Nov 2021 19:40:41 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:55348 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229684AbhKBXkk (ORCPT ); Tue, 2 Nov 2021 19:40:40 -0400 Received: from mail-qv1-xf2e.google.com (mail-qv1-xf2e.google.com [IPv6:2607:f8b0:4864:20::f2e]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 655A6C061714; Tue, 2 Nov 2021 16:38:05 -0700 (PDT) Received: by mail-qv1-xf2e.google.com with SMTP id a24so734054qvb.5; Tue, 02 Nov 2021 16:38:05 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20210112; h=message-id:date:mime-version:user-agent:subject:content-language:to :cc:references:from:in-reply-to:content-transfer-encoding; bh=VDFUI6+9Gqle4Fl3GuOcqR9GGqL6hKFREJxfpi8AcUg=; b=DWclfIX0rDqNx+2O/T+hKL5tIPSEoGQxWRd3THANNkvDydCU3FkXzg2qmZDK/IJEgS pYzQB8gDR9PeLDzxiIZLvHya59tfFQLn/IBO5UW8vyr+tZmbHAAGGfvFSAn/ANu2XtLu AbvSadfIhQlpm/mG+J2lnVlL8Rf46Rx0LRn+Ns+mxvSgtNV/9UQ1bnQRakIJnflPNy/K qDrVNBV9ptlFTeUbzeNzNpqe74l1a+ZCd/JUNIuCUgGxQg7wKWmNFUTjHkMt2exeWbMS yIRLC+QkddF7lAZ7DBrTcaO784Zp/AnPgoJdHO7zkY54iOTF6yWt4yX0InDBlt0Kdz4V ezkA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20210112; h=x-gm-message-state:message-id:date:mime-version:user-agent:subject :content-language:to:cc:references:from:in-reply-to :content-transfer-encoding; bh=VDFUI6+9Gqle4Fl3GuOcqR9GGqL6hKFREJxfpi8AcUg=; b=4jdekJXO6V9Hxu+LefVOfBoYuw1mOSszYUEul2KFzAB1N3GpXrJaU6FLdrLOg6+rvg d9EQkArzgn+6NMwfTIsE8xgOMsW2fUSSOEPZfakHItlIvDEF7dBrqP4tr1RIpjFDtiU1 1uV7OSr+V4LlFZt2RuNLIZcqJqA12lBiuehxZu035CY2vdNqMMIDb2hCog/+RPcvY7Eh oqikbV1AXbV7Fe8f6VDSF9iVN643GnseVpECPpu01Uu5ic4BEmQIptaG9XvrbEwM70g7 XlBXhNXmdGY6VSKnGzGFLM//MlgpaZQYd66c2b2y4VdJ/tszic33hTDknO9uFdE1YtNC VubQ== X-Gm-Message-State: AOAM533S/N4QuYdNeCd4Gi2Z1mR2EbwBd9xTBiAaxGAi7CiplowV1uup ckwTD9zVQySZjFWpppJXviM= X-Google-Smtp-Source: ABdhPJxZ9E6SGKd4V2qIEhjfOAf1okxxeTzu4O+sd/JwEx3NZ1FjLuwJ3N9jwneBbIQUfOi0xTWATQ== X-Received: by 2002:a0c:ecc7:: with SMTP id o7mr8789778qvq.46.1635896284646; Tue, 02 Nov 2021 16:38:04 -0700 (PDT) Received: from [10.4.10.38] (146-115-144-188.s4282.c3-0.nwt-cbr1.sbo-nwt.ma.cable.rcncustomer.com. [146.115.144.188]) by smtp.gmail.com with ESMTPSA id n15sm354561qkp.102.2021.11.02.16.38.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Nov 2021 16:38:04 -0700 (PDT) Message-ID: <9d480d93-c350-f219-e069-d12e16dabb13@gmail.com> Date: Tue, 2 Nov 2021 19:38:02 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.1 Subject: Re: [PATCH v2 07/13] clk: imx: Add initial support for i.MXRT clock driver Content-Language: en-US To: Fabio Estevam List-Id: Cc: NXP Linux Team , Michael Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Sascha Hauer , Ulf Hansson , Dong Aisheng , Stefan Agner , Linus Walleij , Greg Kroah-Hartman , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King - ARM Linux , Abel Vesa , Adrian Hunter , Jiri Slaby , Giulio Benetti , Nobuhiro Iwamatsu , linux-clk , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-kernel , linux-mmc , "open list:GPIO SUBSYSTEM" , linux-serial@vger.kernel.org References: <20211102225701.98944-1-Mr.Bossman075@gmail.com> <20211102225701.98944-8-Mr.Bossman075@gmail.com> From: Jesse Taube In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-gpio@vger.kernel.org Message-ID: <20211102233802.WfDCNGffk58qlt5tlNCg3YBYwVGihcFq1oCwGnshuSA@z> On 11/2/21 19:34, Fabio Estevam wrote: > On Tue, Nov 2, 2021 at 7:57 PM Jesse Taube wrote: > >> +#include "clk.h" This is necessary for the indices. >> +#define ANATOP_BASE_ADDR 0x400d8000 OOPs my bad will fix. > > This is now unused. Please remove it. > >> + clk[IMXRT1050_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2); >> + clk[IMXRT1050_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); >> + clk[IMXRT1050_CLK_LPUART1] = imx_clk_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); >> + clk[IMXRT1050_CLK_LCDIF_APB] = imx_clk_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10); >> + clk[IMXRT1050_CLK_DMA] = imx_clk_gate("dma", "ipg", ccm_base + 0x7C, 6); >> + clk[IMXRT1050_CLK_DMA_MUX] = imx_clk_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); > > The imx clock drivers have been converted to the clk_hw API. > Oh will do, didn't know this. > For a reference, please check: > f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API") > > The same conversion could be done here. > >> + imx_check_clocks(clk, ARRAY_SIZE(clk)); >> + clk_data.clks = clk; >> + clk_data.clk_num = ARRAY_SIZE(clk); >> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL1_ARM]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL2_SYS]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL3_USB_OTG]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL3_PFD1_664_62M]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL2_PFD2_396M]); > > If these clocks are essential for the SoC to work, then you could pass > the CLK_IS_CRITICAL flag instead of calling clk_prepare_enable() > I'll look into that Thx From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 7E446C433F5 for ; Tue, 2 Nov 2021 23:39:27 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4A12260FC2 for ; Tue, 2 Nov 2021 23:39:27 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 4A12260FC2 Authentication-Results: mail.kernel.org; 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[146.115.144.188]) by smtp.gmail.com with ESMTPSA id n15sm354561qkp.102.2021.11.02.16.38.03 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 02 Nov 2021 16:38:04 -0700 (PDT) Message-ID: <9d480d93-c350-f219-e069-d12e16dabb13@gmail.com> Date: Tue, 2 Nov 2021 19:38:02 -0400 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.2.1 Subject: Re: [PATCH v2 07/13] clk: imx: Add initial support for i.MXRT clock driver Content-Language: en-US To: Fabio Estevam List-Id: Cc: NXP Linux Team , Michael Turquette , Stephen Boyd , Rob Herring , Shawn Guo , Sascha Hauer , Sascha Hauer , Ulf Hansson , Dong Aisheng , Stefan Agner , Linus Walleij , Greg Kroah-Hartman , Arnd Bergmann , Olof Johansson , soc@kernel.org, Russell King - ARM Linux , Abel Vesa , Adrian Hunter , Jiri Slaby , Giulio Benetti , Nobuhiro Iwamatsu , linux-clk , "open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS" , "moderated list:ARM/FREESCALE IMX / MXC ARM ARCHITECTURE" , linux-kernel , linux-mmc , "open list:GPIO SUBSYSTEM" , linux-serial@vger.kernel.org References: <20211102225701.98944-1-Mr.Bossman075@gmail.com> <20211102225701.98944-8-Mr.Bossman075@gmail.com> From: Jesse Taube In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211102_163805_949628_2A973166 X-CRM114-Status: GOOD ( 19.87 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Message-ID: <20211102233802.lubK8DQkpXZ3ZVF-e2PNnsMMjzaX9QcKF1lbPGLvHeQ@z> On 11/2/21 19:34, Fabio Estevam wrote: > On Tue, Nov 2, 2021 at 7:57 PM Jesse Taube wrote: > >> +#include "clk.h" This is necessary for the indices. >> +#define ANATOP_BASE_ADDR 0x400d8000 OOPs my bad will fix. > > This is now unused. Please remove it. > >> + clk[IMXRT1050_CLK_USDHC1] = imx_clk_gate2("usdhc1", "usdhc1_podf", ccm_base + 0x80, 2); >> + clk[IMXRT1050_CLK_USDHC2] = imx_clk_gate2("usdhc2", "usdhc2_podf", ccm_base + 0x80, 4); >> + clk[IMXRT1050_CLK_LPUART1] = imx_clk_gate2("lpuart1", "lpuart_podf", ccm_base + 0x7c, 24); >> + clk[IMXRT1050_CLK_LCDIF_APB] = imx_clk_gate2("lcdif", "lcdif_podf", ccm_base + 0x74, 10); >> + clk[IMXRT1050_CLK_DMA] = imx_clk_gate("dma", "ipg", ccm_base + 0x7C, 6); >> + clk[IMXRT1050_CLK_DMA_MUX] = imx_clk_gate("dmamux0", "ipg", ccm_base + 0x7C, 7); > > The imx clock drivers have been converted to the clk_hw API. > Oh will do, didn't know this. > For a reference, please check: > f1541e15e38e ("clk: imx6sx: Switch to clk_hw based API") > > The same conversion could be done here. > >> + imx_check_clocks(clk, ARRAY_SIZE(clk)); >> + clk_data.clks = clk; >> + clk_data.clk_num = ARRAY_SIZE(clk); >> + of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL1_ARM]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL2_SYS]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL3_USB_OTG]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL3_PFD1_664_62M]); >> + clk_prepare_enable(clk[IMXRT1050_CLK_PLL2_PFD2_396M]); > > If these clocks are essential for the SoC to work, then you could pass > the CLK_IS_CRITICAL flag instead of calling clk_prepare_enable() > I'll look into that Thx _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel