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Thu, 27 Mar 2025 17:31:25 +0800 (CST) Date: Thu, 27 Mar 2025 17:31:24 +0800 From: Peter Chen To: "Arnd Bergmann" Cc: "Krzysztof Kozlowski" , "Marc Zyngier" , soc@kernel.org, "Rob Herring" , krzk+dt@kernel.org, "Conor Dooley" , "Catalin Marinas" , "Will Deacon" , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, cix-kernel-upstream@cixtech.com, marcin@juszkiewicz.com.pl, kajetan.puchalski@arm.com, "Krzysztof Kozlowski" , "Fugang . duan" Subject: Re: [PATCH v5 5/6] arm64: dts: cix: add initial CIX P1(SKY1) dts support Message-ID: References: <20250324062420.360289-1-peter.chen@cixtech.com> <20250324062420.360289-6-peter.chen@cixtech.com> <865xjxmlgl.wl-maz@kernel.org> <861pukm9yd.wl-maz@kernel.org> <422deb4d-db29-48c1-b0c9-7915951df500@app.fastmail.com> Precedence: bulk X-Mailing-List: soc@lists.linux.dev List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <422deb4d-db29-48c1-b0c9-7915951df500@app.fastmail.com> X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: TY2PEPF0000AB83:EE_|SEYPR06MB5986:EE_ X-MS-Office365-Filtering-Correlation-Id: 4ac0e4e0-db5d-40c4-1faf-08dd6d122589 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|1800799024|36860700013|376014|7416014; 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X-OriginatorOrg: cixtech.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 27 Mar 2025 09:31:26.0716 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 4ac0e4e0-db5d-40c4-1faf-08dd6d122589 X-MS-Exchange-CrossTenant-Id: 0409f77a-e53d-4d23-943e-ccade7cb4811 X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=0409f77a-e53d-4d23-943e-ccade7cb4811;Ip=[222.71.101.198];Helo=[smtprelay.cixcomputing.com] X-MS-Exchange-CrossTenant-AuthSource: TY2PEPF0000AB83.apcprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEYPR06MB5986 On 25-03-27 09:18:42, Arnd Bergmann wrote: > > On Thu, Mar 27, 2025, at 08:16, Krzysztof Kozlowski wrote: > > On 27/03/2025 07:44, Peter Chen wrote: > >>>> On 25-03-25 10:52:10, Marc Zyngier wrote: > >> > >> Thanks for your interesting of our platform, and your comments > >> help us a lot. But I don't think it wastes reviewers and maintainers > >> time, a clean patch set saves everyone's time during upstream process. > >> > >> For how to organize the patch set for SoC, Krzysztof gave good summary > >> at [1]. We are going on upstream [2], this patch set is just a start > >> and base but not like you said for marketing purpose. > > > > > > I do not think I suggested in [1] to ever send new SoC containing only > > CPUs and interrupt controller, without even serial. My instruction [1] > > was how to organize it. The DTS can be even fully complete, see the > > upstreaming example I have been using all the time - Qualcomm SM8650: > > > > https://lore.kernel.org/all/20231124-topic-sm8650-upstream-dt-v4-0-e402e73cc5f0@linaro.org/ > > It is easier if there are other SoCs in the same family that are > already supported than an entire new platform, but we have certainly > done it for new SoC families as well. > > > Entire SoC sent to mailing list on the day one of public release of that > > flagship Qualcomm SoC. The SoC DTSI and board DTS have almost complete > > picture, except few trickier pieces... but it even has full display and > > GPU! Plus, as I explained on my email on samsung-soc, that DTS/DTSI > > patchset references all other bindings with their state, so SoC > > maintainers can understand what is the overall progress and what will be > > the result in DT schema checks, if they apply the patchset. > > > > The minimum, absolute minimum submission is with the serial nodes. I > > would prefer to have some storage or any other interface as well, but > > that's fine. > > Agreed. The usual arrangement for a new SoC family is to have > the minimum set of drivers (uart, clk, pinctrl, regulator, > iommu, irqchip) along with the DT bindings and the dts files > in one branch and have that go through the SoC tree as part of > the soc/newsoc branch. It sounds like in this case we only need > uart and a mailbox since the rest are shared with existing > firmware based drivers, so this isn't even the worst case > but still requires some coordination between subsystem maintainers > to ensure that all patches have been properly reviewed before > I merge them. So, in this case, we should add mailbox driver support in this series, and once the mailbox maintainer has reviewed mailbox driver, all the patches could go your tree? > > Any peripheral drivers that are not essential for booting > (typically mmc, ufs, spi, i2c, gpu, sound, pci) can get > submitted at the same time, as there is no dependency on > the platform being merged first. > Thanks for telling us this. -- Best regards, Peter