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[34.82.65.13]) by smtp.gmail.com with ESMTPSA id m6-20020a170902db0600b001c5fe217fb9sm302800plx.267.2023.10.11.14.49.59 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Oct 2023 14:49:59 -0700 (PDT) Date: Wed, 11 Oct 2023 14:49:56 -0700 From: William McVicker To: Peter Griffin List-Id: Cc: robh+dt@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, conor+dt@kernel.org, sboyd@kernel.org, tomasz.figa@gmail.com, s.nawrocki@samsung.com, linus.walleij@linaro.org, wim@linux-watchdog.org, linux@roeck-us.net, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, olof@lixom.net, gregkh@linuxfoundation.org, cw00.choi@samsung.com, tudor.ambarus@linaro.org, andre.draszik@linaro.org, semen.protsenko@linaro.org, saravanak@google.com, soc@kernel.org, devicetree@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, linux-gpio@vger.kernel.org, linux-watchdog@vger.kernel.org, kernel-team@android.com, linux-serial@vger.kernel.org Subject: Re: [PATCH v3 09/20] clk: samsung: clk-pll: Add support for pll_{0516,0517,518} Message-ID: References: <20231011184823.443959-1-peter.griffin@linaro.org> <20231011184823.443959-10-peter.griffin@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20231011184823.443959-10-peter.griffin@linaro.org> On 10/11/2023, Peter Griffin wrote: > These plls are found in the Tensor gs101 SoC found in the Pixel 6. > > pll0516x: Integer PLL with high frequency > pll0517x: Integer PLL with middle frequency > pll0518x: Integer PLL with low frequency > > PLL0516x > FOUT = (MDIV * 2 * FIN)/PDIV * 2^SDIV) > > PLL0517x and PLL0518x > FOUT = (MDIV * FIN)/PDIV*2^SDIV) > > The PLLs are similar enough to pll_0822x that the same code can handle > both. The main difference is the change in the fout formula for the > high frequency 0516 pll. > > Locktime for 516,517 & 518 is 150 the same as the pll_0822x lock factor. > MDIV, SDIV PDIV masks and bit shifts are also the same as 0822x. > > When defining the PLL the "con" parameter should be set to CON3 > register, like this > > PLL(pll_0517x, CLK_FOUT_SHARED0_PLL, "fout_shared0_pll", "oscclk", > PLL_LOCKTIME_PLL_SHARED0, PLL_CON3_PLL_SHARED0, > NULL), > > Signed-off-by: Peter Griffin Tested-by: Will McVicker Thanks, Will > --- > drivers/clk/samsung/clk-pll.c | 9 ++++++++- > drivers/clk/samsung/clk-pll.h | 3 +++ > 2 files changed, 11 insertions(+), 1 deletion(-) > > diff --git a/drivers/clk/samsung/clk-pll.c b/drivers/clk/samsung/clk-pll.c > index 74934c6182ce..4ef9fea2a425 100644 > --- a/drivers/clk/samsung/clk-pll.c > +++ b/drivers/clk/samsung/clk-pll.c > @@ -442,7 +442,11 @@ static unsigned long samsung_pll0822x_recalc_rate(struct clk_hw *hw, > pdiv = (pll_con3 >> PLL0822X_PDIV_SHIFT) & PLL0822X_PDIV_MASK; > sdiv = (pll_con3 >> PLL0822X_SDIV_SHIFT) & PLL0822X_SDIV_MASK; > > - fvco *= mdiv; > + if (pll->type == pll_0516x) > + fvco = fvco * 2 * mdiv; > + else > + fvco *= mdiv; > + > do_div(fvco, (pdiv << sdiv)); > > return (unsigned long)fvco; > @@ -1316,6 +1320,9 @@ static void __init _samsung_clk_register_pll(struct samsung_clk_provider *ctx, > case pll_1417x: > case pll_0818x: > case pll_0822x: > + case pll_0516x: > + case pll_0517x: > + case pll_0518x: > pll->enable_offs = PLL0822X_ENABLE_SHIFT; > pll->lock_offs = PLL0822X_LOCK_STAT_SHIFT; > if (!pll->rate_table) > diff --git a/drivers/clk/samsung/clk-pll.h b/drivers/clk/samsung/clk-pll.h > index 0725d485c6ee..ffd3d52c0dec 100644 > --- a/drivers/clk/samsung/clk-pll.h > +++ b/drivers/clk/samsung/clk-pll.h > @@ -38,6 +38,9 @@ enum samsung_pll_type { > pll_0822x, > pll_0831x, > pll_142xx, > + pll_0516x, > + pll_0517x, > + pll_0518x, > }; > > #define PLL_RATE(_fin, _m, _p, _s, _k, _ks) \ > -- > 2.42.0.655.g421f12c284-goog >