From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id E1FBFC4332F for ; Sat, 11 Nov 2023 21:33:45 +0000 (UTC) Received: by smtp.kernel.org (Postfix) id 8FBE7C43391; Sat, 11 Nov 2023 21:33:45 +0000 (UTC) Received: from mail-wm1-f54.google.com (mail-wm1-f54.google.com [209.85.128.54]) (using TLSv1.3 with cipher TLS_AES_128_GCM_SHA256 (128/128 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by smtp.kernel.org (Postfix) with ESMTPS id 7784EC433C8; Sat, 11 Nov 2023 21:33:44 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 smtp.kernel.org 7784EC433C8 Authentication-Results: smtp.kernel.org; dmarc=pass (p=none dis=none) header.from=gmail.com Authentication-Results: smtp.kernel.org; spf=pass smtp.mailfrom=gmail.com Received: by mail-wm1-f54.google.com with SMTP id 5b1f17b1804b1-408382da7f0so25426515e9.0; Sat, 11 Nov 2023 13:33:44 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20230601; t=1699738422; x=1700343222; darn=kernel.org; h=mime-version:user-agent:content-transfer-encoding:references :in-reply-to:date:cc:to:from:subject:message-id:from:to:cc:subject :date:message-id:reply-to; bh=BjJpwKGCecxdkQ5LjdaCff64J4ZeBO10oL7F7MwcVn4=; b=SiDr7gQ7WKPE1PJ9Y8O63LbJefF0vxR1HG70c9fYifsHSSzztXjRMk31bN1Lel2AqA OUBHURdRRiGtOt9I0QtQWqcnNnt5OEqREhvrl5wOAKm/OqoVsKklbi6fMpYv+MRmW6rS qK1gMuhis/IUpqppp3iM7/ne+aT4/OX6w7tp3EmTZBbRRnCNwJOtye23kpzJ1CNpTBJ2 wLrZBG4lHkBmfdyKCHXoSZomtX9DGGYg4QOR9J79H+efOCy3lvm/8roQWtmaIEDMDC3l 9dWm5nVvm6Jy9u77AR6PCDktsEGv445xk4MlQiLPNCvmYmy0zQyB7Ecv+rEwBF2sYr1Q RUiQ== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20230601; t=1699738422; x=1700343222; h=mime-version:user-agent:content-transfer-encoding:references :in-reply-to:date:cc:to:from:subject:message-id:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=BjJpwKGCecxdkQ5LjdaCff64J4ZeBO10oL7F7MwcVn4=; b=DhH5TzFE0TkPDl9rqMDxDUSi4QEp0YzskY2yxQ54TtMm4Ml7Kf8OL0CBEYGDvnVBUH S2RF7oJyQoMN74LDX9qc2W2+34fDj074BLZaConw8GEZp4so/uxs+4m20MXElpK5rLWu vB2+sTZwYxxUgBflW+FE4fuUNeVZ4wSoC4PqgwkU1hq9B8Xe6I+zdI8cz7ONiv3CvI2h o2Zmges+Y4Ebrw+ai16joFSts7/dT3qSQUIfKK3o15DQOYdq8hchBxCD0oXQew3fyuOO 04ILL5Use7S4mSMSreQgSPhvlEUR4FMLS6Z2LDyRonDXTfMFrl2Ocg2cTOK+Fp70zgRj WC7g== X-Gm-Message-State: AOJu0Yy2hjMV7MEMvpl5doozn8HUhGtqbbK4Et7ATxtIDhHZMFmnOClZ 1A+FpIinaExgDdVZkZnyKbwZMLWABxrFLA== X-Google-Smtp-Source: AGHT+IGcspAIBmQE8uECroiT5zYPxAfvcuIKjKOjZDZOhwNchFn+oYO8zOgLHmFyk1hPD+Lg8347oA== X-Received: by 2002:a05:600c:5121:b0:408:57bb:ef96 with SMTP id o33-20020a05600c512100b0040857bbef96mr2147252wms.30.1699738422278; Sat, 11 Nov 2023 13:33:42 -0800 (PST) Received: from giga-mm.home ([2a02:1210:8629:800:82ee:73ff:feb8:99e3]) by smtp.gmail.com with ESMTPSA id be14-20020a05600c1e8e00b00401b242e2e6sm8935242wmb.47.2023.11.11.13.33.40 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 11 Nov 2023 13:33:41 -0800 (PST) Message-ID: Subject: Re: [PATCH v3 07/42] soc: Add SoC driver for Cirrus ep93xx From: Alexander Sverdlin To: Andy Shevchenko , nikita.shubin@maquefel.me List-Id: Cc: Hartley Sweeten , Lennert Buytenhek , Russell King , Lukasz Majewski , Linus Walleij , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Michael Turquette , Stephen Boyd , Daniel Lezcano , Thomas Gleixner , Alessandro Zummo , Alexandre Belloni , Wim Van Sebroeck , Guenter Roeck , Sebastian Reichel , Thierry Reding , Uwe =?ISO-8859-1?Q?Kleine-K=F6nig?= , Mark Brown , "David S. Miller" , Eric Dumazet , Jakub Kicinski , Paolo Abeni , Vinod Koul , Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Damien Le Moal , Sergey Shtylyov , Dmitry Torokhov , Arnd Bergmann , Olof Johansson , soc@kernel.org, Liam Girdwood , Jaroslav Kysela , Takashi Iwai , Michael Peters , Kris Bahnsen , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-gpio@vger.kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-rtc@vger.kernel.org, linux-watchdog@vger.kernel.org, linux-pm@vger.kernel.org, linux-pwm@vger.kernel.org, linux-spi@vger.kernel.org, netdev@vger.kernel.org, dmaengine@vger.kernel.org, linux-mtd@lists.infradead.org, linux-ide@vger.kernel.org, linux-input@vger.kernel.org, alsa-devel@alsa-project.org Date: Sat, 11 Nov 2023 22:33:38 +0100 In-Reply-To: References: <20230605-ep93xx-v3-0-3d63a5f1103e@maquefel.me> <20230605-ep93xx-v3-7-3d63a5f1103e@maquefel.me> Content-Type: text/plain; charset="UTF-8" Content-Transfer-Encoding: quoted-printable User-Agent: Evolution 3.48.4 MIME-Version: 1.0 Hello Andy, On Fri, 2023-07-21 at 17:13 +0300, Andy Shevchenko wrote: > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0spin_lock_irqsave(&ep93xx_sw= lock, flags); > > + > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0regmap_read(map, EP93XX_SYSC= ON_DEVCFG, &val); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0val &=3D ~clear_bits; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0val |=3D set_bits; > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0regmap_write(map, EP93XX_SYS= CON_SWLOCK, EP93XX_SWLOCK_MAGICK); > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0regmap_write(map, EP93XX_SYS= CON_DEVCFG, val); >=20 > Is this sequence a must? > I.o.w. can you first supply magic and then update devcfg? >=20 > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0spin_unlock_irqrestore(&ep93= xx_swlock, flags); >=20 > ... >=20 > > +void ep93xx_swlocked_update_bits(struct regmap *map, unsigned int reg, > > +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2= =A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0= =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned int mask, unsigned int = val) > > +{ >=20 > Same Q as above. EP93xx User Manual [1] has most verbose description of SWLock for ADC block: "Writing 0xAA to this register will unlock all locked registers until the next block access. The ARM lock instruction prefix should be used for the two consequtive write cycles when writing to locked chip registers." One may conclude that RmW (two accesses to the particular block) sequence is not appropriate. [1]=C2=A0https://cdn.embeddedts.com/resource-attachments/ts-7000_ep9301-ug.= pdf=20 --=20 Alexander Sverdlin.