[PATCH 0/2] riscv: dts: sophgo: add more sg2042 isa extension support

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* [PATCH 0/2] riscv: dts: sophgo: add more sg2042 isa extension support
@ 2025-05-09 22:11 Han Gao
  2025-05-09 22:11 ` [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree Han Gao
  2025-05-09 22:11 ` [PATCH 2/2] riscv: dts: sophgo: add ziccrse for sg2042 Han Gao
  0 siblings, 2 replies; 12+ messages in thread
From: Han Gao @ 2025-05-09 22:11 UTC (permalink / raw)
  To: devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
	Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Alexandre Ghiti, Han Gao, sophgo, linux-riscv, linux-kernel

Add xtheadvector & ziccrse for sg2042

Thanks,
Han

Han Gao (2):
  riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  riscv: dts: sophgo: add ziccrse for sg2042

 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 320 ++++++++++++--------
 1 file changed, 192 insertions(+), 128 deletions(-)

-- 
2.47.2


^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  2025-05-09 22:11 [PATCH 0/2] riscv: dts: sophgo: add more sg2042 isa extension support Han Gao
@ 2025-05-09 22:11 ` Han Gao
  2025-05-13  1:19   ` Chen Wang
  2025-05-09 22:11 ` [PATCH 2/2] riscv: dts: sophgo: add ziccrse for sg2042 Han Gao
  1 sibling, 1 reply; 12+ messages in thread
From: Han Gao @ 2025-05-09 22:11 UTC (permalink / raw)
  To: devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
	Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Alexandre Ghiti, Han Gao, sophgo, linux-riscv, linux-kernel

The sg2042 SoCs support xtheadvector so it can be included in the
devicetree. Also include vlenb for the cpu.

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
 1 file changed, 128 insertions(+), 64 deletions(-)

diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index b136b6c4128c..927e0260acbd 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -260,7 +260,8 @@ cpu0: cpu@0 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <0>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -285,7 +286,8 @@ cpu1: cpu@1 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <1>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -310,7 +312,8 @@ cpu2: cpu@2 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <2>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -335,7 +338,8 @@ cpu3: cpu@3 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <3>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -360,7 +364,8 @@ cpu4: cpu@4 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <4>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -385,7 +390,8 @@ cpu5: cpu@5 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <5>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -410,7 +416,8 @@ cpu6: cpu@6 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <6>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -435,7 +442,8 @@ cpu7: cpu@7 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <7>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -460,7 +468,8 @@ cpu8: cpu@8 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <8>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -485,7 +494,8 @@ cpu9: cpu@9 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <9>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -510,7 +520,8 @@ cpu10: cpu@10 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <10>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -535,7 +546,8 @@ cpu11: cpu@11 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <11>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -560,7 +572,8 @@ cpu12: cpu@12 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <12>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -585,7 +598,8 @@ cpu13: cpu@13 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <13>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -610,7 +624,8 @@ cpu14: cpu@14 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <14>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -635,7 +650,8 @@ cpu15: cpu@15 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <15>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -660,7 +676,8 @@ cpu16: cpu@16 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <16>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -685,7 +702,8 @@ cpu17: cpu@17 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <17>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -710,7 +728,8 @@ cpu18: cpu@18 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <18>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -735,7 +754,8 @@ cpu19: cpu@19 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <19>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -760,7 +780,8 @@ cpu20: cpu@20 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <20>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -785,7 +806,8 @@ cpu21: cpu@21 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <21>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -810,7 +832,8 @@ cpu22: cpu@22 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <22>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -835,7 +858,8 @@ cpu23: cpu@23 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <23>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -860,7 +884,8 @@ cpu24: cpu@24 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <24>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -885,7 +910,8 @@ cpu25: cpu@25 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <25>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -910,7 +936,8 @@ cpu26: cpu@26 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <26>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -935,7 +962,8 @@ cpu27: cpu@27 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <27>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -960,7 +988,8 @@ cpu28: cpu@28 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <28>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -985,7 +1014,8 @@ cpu29: cpu@29 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <29>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <30>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <31>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <32>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <33>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <34>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <35>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <36>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <37>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <38>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <39>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <40>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <41>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <42>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <43>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <44>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <45>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <46>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <47>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <48>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <49>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <50>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <51>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <52>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <53>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <54>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <55>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <56>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <57>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <58>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <59>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <60>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <61>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <62>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
@@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
 					       "zicntr", "zicsr", "zifencei",
-					       "zihpm";
+					       "zihpm", "xtheadvector";
+			thead,vlenb = <128>;
 			reg = <63>;
 			i-cache-block-size = <64>;
 			i-cache-size = <65536>;
-- 
2.47.2


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  2025-05-09 22:11 ` [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree Han Gao
@ 2025-05-13  1:19   ` Chen Wang
  2025-05-13  4:47     ` Inochi Amaoto
  2025-05-13  6:45     ` Han Gao
  0 siblings, 2 replies; 12+ messages in thread
From: Chen Wang @ 2025-05-13  1:19 UTC (permalink / raw)
  To: Han Gao, devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto,
	Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, sophgo,
	linux-riscv, linux-kernel

Hi，Han,

I tested with this patch and the machine can bootup. But I find when I 
run "cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb", it print 
nothing, though I expect to see 128.

Do you know why?

Regards,

Chen

On 2025/5/10 6:11, Han Gao wrote:
> The sg2042 SoCs support xtheadvector so it can be included in the
> devicetree. Also include vlenb for the cpu.
>
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> ---
>   arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
>   1 file changed, 128 insertions(+), 64 deletions(-)
>
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> index b136b6c4128c..927e0260acbd 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> @@ -260,7 +260,8 @@ cpu0: cpu@0 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <0>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -285,7 +286,8 @@ cpu1: cpu@1 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <1>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -310,7 +312,8 @@ cpu2: cpu@2 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <2>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -335,7 +338,8 @@ cpu3: cpu@3 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <3>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -360,7 +364,8 @@ cpu4: cpu@4 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <4>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -385,7 +390,8 @@ cpu5: cpu@5 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <5>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -410,7 +416,8 @@ cpu6: cpu@6 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <6>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -435,7 +442,8 @@ cpu7: cpu@7 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <7>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -460,7 +468,8 @@ cpu8: cpu@8 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <8>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -485,7 +494,8 @@ cpu9: cpu@9 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <9>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -510,7 +520,8 @@ cpu10: cpu@10 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <10>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -535,7 +546,8 @@ cpu11: cpu@11 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <11>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -560,7 +572,8 @@ cpu12: cpu@12 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <12>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -585,7 +598,8 @@ cpu13: cpu@13 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <13>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -610,7 +624,8 @@ cpu14: cpu@14 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <14>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -635,7 +650,8 @@ cpu15: cpu@15 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <15>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -660,7 +676,8 @@ cpu16: cpu@16 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <16>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -685,7 +702,8 @@ cpu17: cpu@17 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <17>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -710,7 +728,8 @@ cpu18: cpu@18 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <18>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -735,7 +754,8 @@ cpu19: cpu@19 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <19>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -760,7 +780,8 @@ cpu20: cpu@20 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <20>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -785,7 +806,8 @@ cpu21: cpu@21 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <21>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -810,7 +832,8 @@ cpu22: cpu@22 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <22>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -835,7 +858,8 @@ cpu23: cpu@23 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <23>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -860,7 +884,8 @@ cpu24: cpu@24 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <24>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -885,7 +910,8 @@ cpu25: cpu@25 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <25>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -910,7 +936,8 @@ cpu26: cpu@26 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <26>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -935,7 +962,8 @@ cpu27: cpu@27 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <27>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -960,7 +988,8 @@ cpu28: cpu@28 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <28>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -985,7 +1014,8 @@ cpu29: cpu@29 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <29>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <30>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <31>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <32>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <33>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <34>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <35>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <36>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <37>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <38>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <39>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <40>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <41>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <42>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <43>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <44>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <45>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <46>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <47>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <48>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <49>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <50>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <51>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <52>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <53>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <54>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <55>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <56>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <57>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <58>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <59>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <60>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <61>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <62>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;
> @@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
>   			riscv,isa-base = "rv64i";
>   			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>   					       "zicntr", "zicsr", "zifencei",
> -					       "zihpm";
> +					       "zihpm", "xtheadvector";
> +			thead,vlenb = <128>;
>   			reg = <63>;
>   			i-cache-block-size = <64>;
>   			i-cache-size = <65536>;

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  2025-05-13  1:19   ` Chen Wang
@ 2025-05-13  4:47     ` Inochi Amaoto
  2025-05-13  6:45     ` Han Gao
  1 sibling, 0 replies; 12+ messages in thread
From: Inochi Amaoto @ 2025-05-13  4:47 UTC (permalink / raw)
  To: Chen Wang, Han Gao, devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto,
	Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, sophgo,
	linux-riscv, linux-kernel

On Tue, May 13, 2025 at 09:19:07AM +0800, Chen Wang wrote:
> Hi，Han,
> 
> I tested with this patch and the machine can bootup. But I find when I run
> "cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb", it print nothing,
> though I expect to see 128.
> 
> Do you know why?
> 

Maybe this is a hex number? Do you try hexdump?

Regards,
Inochi

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  2025-05-13  1:19   ` Chen Wang
  2025-05-13  4:47     ` Inochi Amaoto
@ 2025-05-13  6:45     ` Han Gao
  2025-05-13  8:06       ` Chen Wang
  1 sibling, 1 reply; 12+ messages in thread
From: Han Gao @ 2025-05-13  6:45 UTC (permalink / raw)
  To: Chen Wang, devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto,
	Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, sophgo,
	linux-riscv, linux-kernel

You can use xxd to convert it.

cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb | xxd
00000000: 0000 0080                                ....

Regards,
Han

On Tue, May 13, 2025 at 9:19 AM Chen Wang <unicorn_wang@outlook.com> wrote:
>
> Hi，Han,
>
> I tested with this patch and the machine can bootup. But I find when I
> run "cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb", it print
> nothing, though I expect to see 128.
>
> Do you know why?
>
> Regards,
>
> Chen
>
> On 2025/5/10 6:11, Han Gao wrote:
> > The sg2042 SoCs support xtheadvector so it can be included in the
> > devicetree. Also include vlenb for the cpu.
> >
> > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> > ---
> >   arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
> >   1 file changed, 128 insertions(+), 64 deletions(-)
> >
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > index b136b6c4128c..927e0260acbd 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > @@ -260,7 +260,8 @@ cpu0: cpu@0 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <0>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -285,7 +286,8 @@ cpu1: cpu@1 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <1>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -310,7 +312,8 @@ cpu2: cpu@2 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <2>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -335,7 +338,8 @@ cpu3: cpu@3 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <3>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -360,7 +364,8 @@ cpu4: cpu@4 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <4>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -385,7 +390,8 @@ cpu5: cpu@5 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <5>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -410,7 +416,8 @@ cpu6: cpu@6 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <6>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -435,7 +442,8 @@ cpu7: cpu@7 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <7>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -460,7 +468,8 @@ cpu8: cpu@8 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <8>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -485,7 +494,8 @@ cpu9: cpu@9 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <9>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -510,7 +520,8 @@ cpu10: cpu@10 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <10>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -535,7 +546,8 @@ cpu11: cpu@11 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <11>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -560,7 +572,8 @@ cpu12: cpu@12 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <12>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -585,7 +598,8 @@ cpu13: cpu@13 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <13>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -610,7 +624,8 @@ cpu14: cpu@14 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <14>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -635,7 +650,8 @@ cpu15: cpu@15 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <15>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -660,7 +676,8 @@ cpu16: cpu@16 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <16>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -685,7 +702,8 @@ cpu17: cpu@17 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <17>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -710,7 +728,8 @@ cpu18: cpu@18 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <18>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -735,7 +754,8 @@ cpu19: cpu@19 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <19>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -760,7 +780,8 @@ cpu20: cpu@20 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <20>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -785,7 +806,8 @@ cpu21: cpu@21 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <21>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -810,7 +832,8 @@ cpu22: cpu@22 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <22>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -835,7 +858,8 @@ cpu23: cpu@23 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <23>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -860,7 +884,8 @@ cpu24: cpu@24 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <24>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -885,7 +910,8 @@ cpu25: cpu@25 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <25>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -910,7 +936,8 @@ cpu26: cpu@26 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <26>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -935,7 +962,8 @@ cpu27: cpu@27 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <27>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -960,7 +988,8 @@ cpu28: cpu@28 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <28>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -985,7 +1014,8 @@ cpu29: cpu@29 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <29>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <30>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <31>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <32>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <33>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <34>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <35>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <36>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <37>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <38>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <39>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <40>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <41>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <42>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <43>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <44>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <45>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <46>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <47>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <48>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <49>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <50>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <51>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <52>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <53>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <54>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <55>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <56>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <57>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <58>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <59>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <60>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <61>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <62>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;
> > @@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
> >                       riscv,isa-base = "rv64i";
> >                       riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >                                              "zicntr", "zicsr", "zifencei",
> > -                                            "zihpm";
> > +                                            "zihpm", "xtheadvector";
> > +                     thead,vlenb = <128>;
> >                       reg = <63>;
> >                       i-cache-block-size = <64>;
> >                       i-cache-size = <65536>;

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  2025-05-13  6:45     ` Han Gao
@ 2025-05-13  8:06       ` Chen Wang
  2025-05-13  9:13         ` Han Gao
  0 siblings, 1 reply; 12+ messages in thread
From: Chen Wang @ 2025-05-13  8:06 UTC (permalink / raw)
  To: Han Gao, devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto,
	Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, sophgo,
	linux-riscv, linux-kernel


On 2025/5/13 14:45, Han Gao wrote:
> You can use xxd to convert it.
>
> cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb | xxd
> 00000000: 0000 0080                                ....
>
> Regards,
> Han

I can read this after disable ERRATA_THEAD_GHOSTWRITE.

I recommend adding some explanation notes in the commit message. For 
example, when we need to enable xtheadvector, the prerequisite is to 
turn off "ERRATA_THEAD_GHOSTWRITE".
I found the relevant patch is 
https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com/, 
also hope adding this will help later people quickly understand and 
avoid my mistakes.

One more question is about writing value of "thead,vlenb". See bindings 
description in Documentation/devicetree/bindings/riscv/cpus.yaml:

```

   thead,vlenb:
     $ref: /schemas/types.yaml#/definitions/uint32
     description:
       VLEN/8, the vector register length in bytes. This property is 
required on
       thead systems where the vector register length is not identical 
on all harts, or
       the vlenb CSR is not available.

```

What I am not sure about is whether we should write 128 or 128/8=16? 
Assuming VLEN of C910 is 128bit.

Thanks,

Chen

>
> On Tue, May 13, 2025 at 9:19 AM Chen Wang <unicorn_wang@outlook.com> wrote:
>> Hi，Han,
>>
>> I tested with this patch and the machine can bootup. But I find when I
>> run "cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb", it print
>> nothing, though I expect to see 128.
>>
>> Do you know why?
>>
>> Regards,
>>
>> Chen
>>
>> On 2025/5/10 6:11, Han Gao wrote:
>>> The sg2042 SoCs support xtheadvector so it can be included in the
>>> devicetree. Also include vlenb for the cpu.
>>>
>>> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
>>> ---
>>>    arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
>>>    1 file changed, 128 insertions(+), 64 deletions(-)
>>>
>>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> index b136b6c4128c..927e0260acbd 100644
>>> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>> @@ -260,7 +260,8 @@ cpu0: cpu@0 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <0>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -285,7 +286,8 @@ cpu1: cpu@1 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <1>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -310,7 +312,8 @@ cpu2: cpu@2 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <2>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -335,7 +338,8 @@ cpu3: cpu@3 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <3>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -360,7 +364,8 @@ cpu4: cpu@4 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <4>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -385,7 +390,8 @@ cpu5: cpu@5 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <5>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -410,7 +416,8 @@ cpu6: cpu@6 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <6>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -435,7 +442,8 @@ cpu7: cpu@7 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <7>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -460,7 +468,8 @@ cpu8: cpu@8 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <8>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -485,7 +494,8 @@ cpu9: cpu@9 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <9>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -510,7 +520,8 @@ cpu10: cpu@10 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <10>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -535,7 +546,8 @@ cpu11: cpu@11 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <11>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -560,7 +572,8 @@ cpu12: cpu@12 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <12>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -585,7 +598,8 @@ cpu13: cpu@13 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <13>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -610,7 +624,8 @@ cpu14: cpu@14 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <14>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -635,7 +650,8 @@ cpu15: cpu@15 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <15>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -660,7 +676,8 @@ cpu16: cpu@16 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <16>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -685,7 +702,8 @@ cpu17: cpu@17 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <17>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -710,7 +728,8 @@ cpu18: cpu@18 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <18>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -735,7 +754,8 @@ cpu19: cpu@19 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <19>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -760,7 +780,8 @@ cpu20: cpu@20 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <20>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -785,7 +806,8 @@ cpu21: cpu@21 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <21>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -810,7 +832,8 @@ cpu22: cpu@22 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <22>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -835,7 +858,8 @@ cpu23: cpu@23 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <23>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -860,7 +884,8 @@ cpu24: cpu@24 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <24>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -885,7 +910,8 @@ cpu25: cpu@25 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <25>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -910,7 +936,8 @@ cpu26: cpu@26 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <26>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -935,7 +962,8 @@ cpu27: cpu@27 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <27>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -960,7 +988,8 @@ cpu28: cpu@28 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <28>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -985,7 +1014,8 @@ cpu29: cpu@29 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <29>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <30>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <31>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <32>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <33>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <34>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <35>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <36>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <37>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <38>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <39>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <40>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <41>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <42>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <43>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <44>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <45>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <46>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <47>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <48>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <49>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <50>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <51>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <52>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <53>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <54>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <55>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <56>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <57>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <58>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <59>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <60>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <61>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <62>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;
>>> @@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
>>>                        riscv,isa-base = "rv64i";
>>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>                                               "zicntr", "zicsr", "zifencei",
>>> -                                            "zihpm";
>>> +                                            "zihpm", "xtheadvector";
>>> +                     thead,vlenb = <128>;
>>>                        reg = <63>;
>>>                        i-cache-block-size = <64>;
>>>                        i-cache-size = <65536>;

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  2025-05-13  8:06       ` Chen Wang
@ 2025-05-13  9:13         ` Han Gao
  2025-05-13 10:05           ` Chen Wang
  0 siblings, 1 reply; 12+ messages in thread
From: Han Gao @ 2025-05-13  9:13 UTC (permalink / raw)
  To: Chen Wang, devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto,
	Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, sophgo,
	linux-riscv, linux-kernel

> Assuming VLEN of C910 is 128bit.

I refer to the value of c906 because c906 and c910/c920v1 have the same value.

Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com/
[1]

On Tue, May 13, 2025 at 4:06 PM Chen Wang <unicorn_wang@outlook.com> wrote:
>
>
> On 2025/5/13 14:45, Han Gao wrote:
> > You can use xxd to convert it.
> >
> > cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb | xxd
> > 00000000: 0000 0080                                ....
> >
> > Regards,
> > Han
>
> I can read this after disable ERRATA_THEAD_GHOSTWRITE.
>
> I recommend adding some explanation notes in the commit message. For
> example, when we need to enable xtheadvector, the prerequisite is to
> turn off "ERRATA_THEAD_GHOSTWRITE".
> I found the relevant patch is
> https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com/,
> also hope adding this will help later people quickly understand and
> avoid my mistakes.
>
> One more question is about writing value of "thead,vlenb". See bindings
> description in Documentation/devicetree/bindings/riscv/cpus.yaml:
>
> ```
>
>    thead,vlenb:
>      $ref: /schemas/types.yaml#/definitions/uint32
>      description:
>        VLEN/8, the vector register length in bytes. This property is
> required on
>        thead systems where the vector register length is not identical
> on all harts, or
>        the vlenb CSR is not available.
>
> ```
>
> What I am not sure about is whether we should write 128 or 128/8=16?
> Assuming VLEN of C910 is 128bit.
>
> Thanks,
>
> Chen
>
> >
> > On Tue, May 13, 2025 at 9:19 AM Chen Wang <unicorn_wang@outlook.com> wrote:
> >> Hi，Han,
> >>
> >> I tested with this patch and the machine can bootup. But I find when I
> >> run "cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb", it print
> >> nothing, though I expect to see 128.
> >>
> >> Do you know why?
> >>
> >> Regards,
> >>
> >> Chen
> >>
> >> On 2025/5/10 6:11, Han Gao wrote:
> >>> The sg2042 SoCs support xtheadvector so it can be included in the
> >>> devicetree. Also include vlenb for the cpu.
> >>>
> >>> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> >>> ---
> >>>    arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
> >>>    1 file changed, 128 insertions(+), 64 deletions(-)
> >>>
> >>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> >>> index b136b6c4128c..927e0260acbd 100644
> >>> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> >>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> >>> @@ -260,7 +260,8 @@ cpu0: cpu@0 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <0>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -285,7 +286,8 @@ cpu1: cpu@1 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <1>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -310,7 +312,8 @@ cpu2: cpu@2 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <2>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -335,7 +338,8 @@ cpu3: cpu@3 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <3>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -360,7 +364,8 @@ cpu4: cpu@4 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <4>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -385,7 +390,8 @@ cpu5: cpu@5 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <5>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -410,7 +416,8 @@ cpu6: cpu@6 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <6>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -435,7 +442,8 @@ cpu7: cpu@7 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <7>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -460,7 +468,8 @@ cpu8: cpu@8 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <8>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -485,7 +494,8 @@ cpu9: cpu@9 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <9>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -510,7 +520,8 @@ cpu10: cpu@10 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <10>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -535,7 +546,8 @@ cpu11: cpu@11 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <11>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -560,7 +572,8 @@ cpu12: cpu@12 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <12>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -585,7 +598,8 @@ cpu13: cpu@13 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <13>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -610,7 +624,8 @@ cpu14: cpu@14 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <14>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -635,7 +650,8 @@ cpu15: cpu@15 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <15>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -660,7 +676,8 @@ cpu16: cpu@16 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <16>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -685,7 +702,8 @@ cpu17: cpu@17 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <17>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -710,7 +728,8 @@ cpu18: cpu@18 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <18>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -735,7 +754,8 @@ cpu19: cpu@19 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <19>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -760,7 +780,8 @@ cpu20: cpu@20 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <20>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -785,7 +806,8 @@ cpu21: cpu@21 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <21>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -810,7 +832,8 @@ cpu22: cpu@22 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <22>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -835,7 +858,8 @@ cpu23: cpu@23 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <23>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -860,7 +884,8 @@ cpu24: cpu@24 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <24>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -885,7 +910,8 @@ cpu25: cpu@25 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <25>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -910,7 +936,8 @@ cpu26: cpu@26 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <26>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -935,7 +962,8 @@ cpu27: cpu@27 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <27>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -960,7 +988,8 @@ cpu28: cpu@28 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <28>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -985,7 +1014,8 @@ cpu29: cpu@29 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <29>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <30>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <31>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <32>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <33>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <34>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <35>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <36>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <37>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <38>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <39>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <40>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <41>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <42>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <43>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <44>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <45>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <46>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <47>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <48>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <49>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <50>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <51>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <52>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <53>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <54>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <55>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <56>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <57>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <58>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <59>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <60>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <61>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <62>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;
> >>> @@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
> >>>                        riscv,isa-base = "rv64i";
> >>>                        riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> >>>                                               "zicntr", "zicsr", "zifencei",
> >>> -                                            "zihpm";
> >>> +                                            "zihpm", "xtheadvector";
> >>> +                     thead,vlenb = <128>;
> >>>                        reg = <63>;
> >>>                        i-cache-block-size = <64>;
> >>>                        i-cache-size = <65536>;

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  2025-05-13  9:13         ` Han Gao
@ 2025-05-13 10:05           ` Chen Wang
  2025-05-13 21:25             ` Charlie Jenkins
  0 siblings, 1 reply; 12+ messages in thread
From: Chen Wang @ 2025-05-13 10:05 UTC (permalink / raw)
  To: Han Gao, devicetree, charlie
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Inochi Amaoto,
	Paul Walmsley, Palmer Dabbelt, Albert Ou, Alexandre Ghiti, sophgo,
	linux-riscv, linux-kernel

Adding Charlie.

Hi, Charlie,

Can you please help confirm this? Is there something wrong with my 
understanding? Copied here below for your quick reference:

> One more question is about writing value of "thead,vlenb". See bindings
> description in Documentation/devicetree/bindings/riscv/cpus.yaml:
> 
> ```
> 
>    thead,vlenb:
>      $ref: /schemas/types.yaml#/definitions/uint32
>      description:
>        VLEN/8, the vector register length in bytes. This property is
> required on
>        thead systems where the vector register length is not identical
> on all harts, or
>        the vlenb CSR is not available.
> 
> ```
> 
> What I am not sure about is whether we should write 128 or 128/8=16?
> Assuming VLEN of C910 is 128bit.


Thanks, Chen

On 2025/5/13 17:13, Han Gao wrote:
>> Assuming VLEN of C910 is 128bit.
> I refer to the value of c906 because c906 and c910/c920v1 have the same value.
>
> Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com/
> [1]
>
> On Tue, May 13, 2025 at 4:06 PM Chen Wang <unicorn_wang@outlook.com> wrote:
>>
>> On 2025/5/13 14:45, Han Gao wrote:
>>> You can use xxd to convert it.
>>>
>>> cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb | xxd
>>> 00000000: 0000 0080                                ....
>>>
>>> Regards,
>>> Han
>> I can read this after disable ERRATA_THEAD_GHOSTWRITE.
>>
>> I recommend adding some explanation notes in the commit message. For
>> example, when we need to enable xtheadvector, the prerequisite is to
>> turn off "ERRATA_THEAD_GHOSTWRITE".
>> I found the relevant patch is
>> https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com/,
>> also hope adding this will help later people quickly understand and
>> avoid my mistakes.
>>
>> One more question is about writing value of "thead,vlenb". See bindings
>> description in Documentation/devicetree/bindings/riscv/cpus.yaml:
>>
>> ```
>>
>>     thead,vlenb:
>>       $ref: /schemas/types.yaml#/definitions/uint32
>>       description:
>>         VLEN/8, the vector register length in bytes. This property is
>> required on
>>         thead systems where the vector register length is not identical
>> on all harts, or
>>         the vlenb CSR is not available.
>>
>> ```
>>
>> What I am not sure about is whether we should write 128 or 128/8=16?
>> Assuming VLEN of C910 is 128bit.
>>
>> Thanks,
>>
>> Chen
>>
>>> On Tue, May 13, 2025 at 9:19 AM Chen Wang <unicorn_wang@outlook.com> wrote:
>>>> Hi，Han,
>>>>
>>>> I tested with this patch and the machine can bootup. But I find when I
>>>> run "cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb", it print
>>>> nothing, though I expect to see 128.
>>>>
>>>> Do you know why?
>>>>
>>>> Regards,
>>>>
>>>> Chen
>>>>
>>>> On 2025/5/10 6:11, Han Gao wrote:
>>>>> The sg2042 SoCs support xtheadvector so it can be included in the
>>>>> devicetree. Also include vlenb for the cpu.
>>>>>
>>>>> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
>>>>> ---
>>>>>     arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 192 +++++++++++++-------
>>>>>     1 file changed, 128 insertions(+), 64 deletions(-)
>>>>>
>>>>> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>>>> index b136b6c4128c..927e0260acbd 100644
>>>>> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>>>> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
>>>>> @@ -260,7 +260,8 @@ cpu0: cpu@0 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <0>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -285,7 +286,8 @@ cpu1: cpu@1 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <1>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -310,7 +312,8 @@ cpu2: cpu@2 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <2>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -335,7 +338,8 @@ cpu3: cpu@3 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <3>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -360,7 +364,8 @@ cpu4: cpu@4 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <4>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -385,7 +390,8 @@ cpu5: cpu@5 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <5>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -410,7 +416,8 @@ cpu6: cpu@6 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <6>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -435,7 +442,8 @@ cpu7: cpu@7 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <7>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -460,7 +468,8 @@ cpu8: cpu@8 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <8>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -485,7 +494,8 @@ cpu9: cpu@9 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <9>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -510,7 +520,8 @@ cpu10: cpu@10 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <10>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -535,7 +546,8 @@ cpu11: cpu@11 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <11>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -560,7 +572,8 @@ cpu12: cpu@12 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <12>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -585,7 +598,8 @@ cpu13: cpu@13 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <13>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -610,7 +624,8 @@ cpu14: cpu@14 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <14>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -635,7 +650,8 @@ cpu15: cpu@15 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <15>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -660,7 +676,8 @@ cpu16: cpu@16 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <16>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -685,7 +702,8 @@ cpu17: cpu@17 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <17>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -710,7 +728,8 @@ cpu18: cpu@18 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <18>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -735,7 +754,8 @@ cpu19: cpu@19 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <19>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -760,7 +780,8 @@ cpu20: cpu@20 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <20>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -785,7 +806,8 @@ cpu21: cpu@21 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <21>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -810,7 +832,8 @@ cpu22: cpu@22 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <22>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -835,7 +858,8 @@ cpu23: cpu@23 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <23>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -860,7 +884,8 @@ cpu24: cpu@24 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <24>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -885,7 +910,8 @@ cpu25: cpu@25 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <25>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -910,7 +936,8 @@ cpu26: cpu@26 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <26>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -935,7 +962,8 @@ cpu27: cpu@27 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <27>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -960,7 +988,8 @@ cpu28: cpu@28 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <28>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -985,7 +1014,8 @@ cpu29: cpu@29 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <29>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1010,7 +1040,8 @@ cpu30: cpu@30 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <30>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1035,7 +1066,8 @@ cpu31: cpu@31 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <31>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1060,7 +1092,8 @@ cpu32: cpu@32 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <32>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1085,7 +1118,8 @@ cpu33: cpu@33 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <33>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1110,7 +1144,8 @@ cpu34: cpu@34 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <34>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1135,7 +1170,8 @@ cpu35: cpu@35 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <35>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1160,7 +1196,8 @@ cpu36: cpu@36 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <36>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1185,7 +1222,8 @@ cpu37: cpu@37 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <37>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1210,7 +1248,8 @@ cpu38: cpu@38 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <38>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1235,7 +1274,8 @@ cpu39: cpu@39 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <39>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1260,7 +1300,8 @@ cpu40: cpu@40 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <40>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1285,7 +1326,8 @@ cpu41: cpu@41 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <41>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1310,7 +1352,8 @@ cpu42: cpu@42 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <42>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1335,7 +1378,8 @@ cpu43: cpu@43 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <43>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1360,7 +1404,8 @@ cpu44: cpu@44 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <44>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1385,7 +1430,8 @@ cpu45: cpu@45 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <45>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1410,7 +1456,8 @@ cpu46: cpu@46 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <46>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1435,7 +1482,8 @@ cpu47: cpu@47 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <47>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1460,7 +1508,8 @@ cpu48: cpu@48 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <48>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1485,7 +1534,8 @@ cpu49: cpu@49 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <49>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1510,7 +1560,8 @@ cpu50: cpu@50 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <50>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1535,7 +1586,8 @@ cpu51: cpu@51 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <51>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1560,7 +1612,8 @@ cpu52: cpu@52 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <52>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1585,7 +1638,8 @@ cpu53: cpu@53 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <53>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1610,7 +1664,8 @@ cpu54: cpu@54 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <54>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1635,7 +1690,8 @@ cpu55: cpu@55 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <55>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1660,7 +1716,8 @@ cpu56: cpu@56 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <56>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1685,7 +1742,8 @@ cpu57: cpu@57 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <57>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1710,7 +1768,8 @@ cpu58: cpu@58 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <58>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1735,7 +1794,8 @@ cpu59: cpu@59 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <59>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1760,7 +1820,8 @@ cpu60: cpu@60 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <60>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1785,7 +1846,8 @@ cpu61: cpu@61 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <61>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1810,7 +1872,8 @@ cpu62: cpu@62 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <62>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;
>>>>> @@ -1835,7 +1898,8 @@ cpu63: cpu@63 {
>>>>>                         riscv,isa-base = "rv64i";
>>>>>                         riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
>>>>>                                                "zicntr", "zicsr", "zifencei",
>>>>> -                                            "zihpm";
>>>>> +                                            "zihpm", "xtheadvector";
>>>>> +                     thead,vlenb = <128>;
>>>>>                         reg = <63>;
>>>>>                         i-cache-block-size = <64>;
>>>>>                         i-cache-size = <65536>;

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree
  2025-05-13 10:05           ` Chen Wang
@ 2025-05-13 21:25             ` Charlie Jenkins
  0 siblings, 0 replies; 12+ messages in thread
From: Charlie Jenkins @ 2025-05-13 21:25 UTC (permalink / raw)
  To: Chen Wang
  Cc: Han Gao, devicetree, Rob Herring, Krzysztof Kozlowski,
	Conor Dooley, Inochi Amaoto, Paul Walmsley, Palmer Dabbelt,
	Albert Ou, Alexandre Ghiti, sophgo, linux-riscv, linux-kernel

On Tue, May 13, 2025 at 06:05:20PM +0800, Chen Wang wrote:
> Adding Charlie.
> 
> Hi, Charlie,
> 
> Can you please help confirm this? Is there something wrong with my
> understanding? Copied here below for your quick reference:
> 
> > One more question is about writing value of "thead,vlenb". See bindings
> > description in Documentation/devicetree/bindings/riscv/cpus.yaml:
> > 
> > ```
> > 
> >    thead,vlenb:
> >      $ref: /schemas/types.yaml#/definitions/uint32
> >      description:
> >        VLEN/8, the vector register length in bytes. This property is
> > required on
> >        thead systems where the vector register length is not identical
> > on all harts, or
> >        the vlenb CSR is not available.
> > 
> > ```
> > 
> > What I am not sure about is whether we should write 128 or 128/8=16?
> > Assuming VLEN of C910 is 128bit.
> 
> 
> Thanks, Chen
> 
> On 2025/5/13 17:13, Han Gao wrote:
> > > Assuming VLEN of C910 is 128bit.
> > I refer to the value of c906 because c906 and c910/c920v1 have the same value.
> > 
> > Link: https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-3-236c22791ef9@rivosinc.com/
> > [1]
> > 
> > On Tue, May 13, 2025 at 4:06 PM Chen Wang <unicorn_wang@outlook.com> wrote:
> > > 
> > > On 2025/5/13 14:45, Han Gao wrote:
> > > > You can use xxd to convert it.
> > > > 
> > > > cat /sys/devices/system/cpu/cpu63/of_node/thead,vlenb | xxd
> > > > 00000000: 0000 0080                                ....
> > > > 
> > > > Regards,
> > > > Han
> > > I can read this after disable ERRATA_THEAD_GHOSTWRITE.

You can also pass "mitigations=off" as a kernel arg.

> > > 
> > > I recommend adding some explanation notes in the commit message. For
> > > example, when we need to enable xtheadvector, the prerequisite is to
> > > turn off "ERRATA_THEAD_GHOSTWRITE".
> > > I found the relevant patch is
> > > https://lore.kernel.org/linux-riscv/20241113-xtheadvector-v11-0-236c22791ef9@rivosinc.com/,
> > > also hope adding this will help later people quickly understand and
> > > avoid my mistakes.
> > > 
> > > One more question is about writing value of "thead,vlenb". See bindings
> > > description in Documentation/devicetree/bindings/riscv/cpus.yaml:
> > > 
> > > ```
> > > 
> > >     thead,vlenb:
> > >       $ref: /schemas/types.yaml#/definitions/uint32
> > >       description:
> > >         VLEN/8, the vector register length in bytes. This property is
> > > required on
> > >         thead systems where the vector register length is not identical
> > > on all harts, or
> > >         the vlenb CSR is not available.
> > > 
> > > ```
> > > 
> > > What I am not sure about is whether we should write 128 or 128/8=16?
> > > Assuming VLEN of C910 is 128bit.

That's a bug. It should 16, but I had put it as 128 for the D1
devicetree.

- Charlie

> > > 
> > > Thanks,
> > > 
> > > Chen
> > > 

^ permalink raw reply	[flat|nested] 12+ messages in thread

* [PATCH 2/2] riscv: dts: sophgo: add ziccrse for sg2042
  2025-05-09 22:11 [PATCH 0/2] riscv: dts: sophgo: add more sg2042 isa extension support Han Gao
  2025-05-09 22:11 ` [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree Han Gao
@ 2025-05-09 22:11 ` Han Gao
  2025-05-09 22:42   ` Inochi Amaoto
  1 sibling, 1 reply; 12+ messages in thread
From: Han Gao @ 2025-05-09 22:11 UTC (permalink / raw)
  To: devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
	Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Alexandre Ghiti, Han Gao, sophgo, linux-riscv, linux-kernel

sg2042 support Ziccrse ISA extension [1].

Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]

Signed-off-by: Han Gao <rabenda.cn@gmail.com>
---
 arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
 1 file changed, 64 insertions(+), 64 deletions(-)

diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
index 927e0260acbd..04a6875574bb 100644
--- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
+++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
@@ -259,7 +259,7 @@ cpu0: cpu@0 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <0>;
@@ -285,7 +285,7 @@ cpu1: cpu@1 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <1>;
@@ -311,7 +311,7 @@ cpu2: cpu@2 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <2>;
@@ -337,7 +337,7 @@ cpu3: cpu@3 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <3>;
@@ -363,7 +363,7 @@ cpu4: cpu@4 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <4>;
@@ -389,7 +389,7 @@ cpu5: cpu@5 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <5>;
@@ -415,7 +415,7 @@ cpu6: cpu@6 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <6>;
@@ -441,7 +441,7 @@ cpu7: cpu@7 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <7>;
@@ -467,7 +467,7 @@ cpu8: cpu@8 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <8>;
@@ -493,7 +493,7 @@ cpu9: cpu@9 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <9>;
@@ -519,7 +519,7 @@ cpu10: cpu@10 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <10>;
@@ -545,7 +545,7 @@ cpu11: cpu@11 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <11>;
@@ -571,7 +571,7 @@ cpu12: cpu@12 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <12>;
@@ -597,7 +597,7 @@ cpu13: cpu@13 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <13>;
@@ -623,7 +623,7 @@ cpu14: cpu@14 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <14>;
@@ -649,7 +649,7 @@ cpu15: cpu@15 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <15>;
@@ -675,7 +675,7 @@ cpu16: cpu@16 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <16>;
@@ -701,7 +701,7 @@ cpu17: cpu@17 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <17>;
@@ -727,7 +727,7 @@ cpu18: cpu@18 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <18>;
@@ -753,7 +753,7 @@ cpu19: cpu@19 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <19>;
@@ -779,7 +779,7 @@ cpu20: cpu@20 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <20>;
@@ -805,7 +805,7 @@ cpu21: cpu@21 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <21>;
@@ -831,7 +831,7 @@ cpu22: cpu@22 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <22>;
@@ -857,7 +857,7 @@ cpu23: cpu@23 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <23>;
@@ -883,7 +883,7 @@ cpu24: cpu@24 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <24>;
@@ -909,7 +909,7 @@ cpu25: cpu@25 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <25>;
@@ -935,7 +935,7 @@ cpu26: cpu@26 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <26>;
@@ -961,7 +961,7 @@ cpu27: cpu@27 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <27>;
@@ -987,7 +987,7 @@ cpu28: cpu@28 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <28>;
@@ -1013,7 +1013,7 @@ cpu29: cpu@29 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <29>;
@@ -1039,7 +1039,7 @@ cpu30: cpu@30 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <30>;
@@ -1065,7 +1065,7 @@ cpu31: cpu@31 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <31>;
@@ -1091,7 +1091,7 @@ cpu32: cpu@32 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <32>;
@@ -1117,7 +1117,7 @@ cpu33: cpu@33 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <33>;
@@ -1143,7 +1143,7 @@ cpu34: cpu@34 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <34>;
@@ -1169,7 +1169,7 @@ cpu35: cpu@35 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <35>;
@@ -1195,7 +1195,7 @@ cpu36: cpu@36 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <36>;
@@ -1221,7 +1221,7 @@ cpu37: cpu@37 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <37>;
@@ -1247,7 +1247,7 @@ cpu38: cpu@38 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <38>;
@@ -1273,7 +1273,7 @@ cpu39: cpu@39 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <39>;
@@ -1299,7 +1299,7 @@ cpu40: cpu@40 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <40>;
@@ -1325,7 +1325,7 @@ cpu41: cpu@41 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <41>;
@@ -1351,7 +1351,7 @@ cpu42: cpu@42 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <42>;
@@ -1377,7 +1377,7 @@ cpu43: cpu@43 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <43>;
@@ -1403,7 +1403,7 @@ cpu44: cpu@44 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <44>;
@@ -1429,7 +1429,7 @@ cpu45: cpu@45 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <45>;
@@ -1455,7 +1455,7 @@ cpu46: cpu@46 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <46>;
@@ -1481,7 +1481,7 @@ cpu47: cpu@47 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <47>;
@@ -1507,7 +1507,7 @@ cpu48: cpu@48 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <48>;
@@ -1533,7 +1533,7 @@ cpu49: cpu@49 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <49>;
@@ -1559,7 +1559,7 @@ cpu50: cpu@50 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <50>;
@@ -1585,7 +1585,7 @@ cpu51: cpu@51 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <51>;
@@ -1611,7 +1611,7 @@ cpu52: cpu@52 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <52>;
@@ -1637,7 +1637,7 @@ cpu53: cpu@53 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <53>;
@@ -1663,7 +1663,7 @@ cpu54: cpu@54 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <54>;
@@ -1689,7 +1689,7 @@ cpu55: cpu@55 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <55>;
@@ -1715,7 +1715,7 @@ cpu56: cpu@56 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <56>;
@@ -1741,7 +1741,7 @@ cpu57: cpu@57 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <57>;
@@ -1767,7 +1767,7 @@ cpu58: cpu@58 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <58>;
@@ -1793,7 +1793,7 @@ cpu59: cpu@59 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <59>;
@@ -1819,7 +1819,7 @@ cpu60: cpu@60 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <60>;
@@ -1845,7 +1845,7 @@ cpu61: cpu@61 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <61>;
@@ -1871,7 +1871,7 @@ cpu62: cpu@62 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <62>;
@@ -1897,7 +1897,7 @@ cpu63: cpu@63 {
 			riscv,isa = "rv64imafdc";
 			riscv,isa-base = "rv64i";
 			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
-					       "zicntr", "zicsr", "zifencei",
+					       "ziccrse", "zicntr", "zicsr", "zifencei",
 					       "zihpm", "xtheadvector";
 			thead,vlenb = <128>;
 			reg = <63>;
-- 
2.47.2


^ permalink raw reply related	[flat|nested] 12+ messages in thread

* Re: [PATCH 2/2] riscv: dts: sophgo: add ziccrse for sg2042
  2025-05-09 22:11 ` [PATCH 2/2] riscv: dts: sophgo: add ziccrse for sg2042 Han Gao
@ 2025-05-09 22:42   ` Inochi Amaoto
  2025-05-10  0:15     ` Inochi Amaoto
  0 siblings, 1 reply; 12+ messages in thread
From: Inochi Amaoto @ 2025-05-09 22:42 UTC (permalink / raw)
  To: Han Gao, devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
	Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Alexandre Ghiti, sophgo, linux-riscv, linux-kernel

On Sat, May 10, 2025 at 06:11:23AM +0800, Han Gao wrote:
> sg2042 support Ziccrse ISA extension [1].
> 
> Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
> 
> Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> ---
>  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
>  1 file changed, 64 insertions(+), 64 deletions(-)
> 
> diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> index 927e0260acbd..04a6875574bb 100644
> --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> @@ -259,7 +259,7 @@ cpu0: cpu@0 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <0>;

I prefer to keep the maximum 74 chars per line. I suggest wrapping
the string. This apply to all the change of this file.

Regards,
Inochi

> @@ -285,7 +285,7 @@ cpu1: cpu@1 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <1>;
> @@ -311,7 +311,7 @@ cpu2: cpu@2 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <2>;
> @@ -337,7 +337,7 @@ cpu3: cpu@3 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <3>;
> @@ -363,7 +363,7 @@ cpu4: cpu@4 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <4>;
> @@ -389,7 +389,7 @@ cpu5: cpu@5 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <5>;
> @@ -415,7 +415,7 @@ cpu6: cpu@6 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <6>;
> @@ -441,7 +441,7 @@ cpu7: cpu@7 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <7>;
> @@ -467,7 +467,7 @@ cpu8: cpu@8 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <8>;
> @@ -493,7 +493,7 @@ cpu9: cpu@9 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <9>;
> @@ -519,7 +519,7 @@ cpu10: cpu@10 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <10>;
> @@ -545,7 +545,7 @@ cpu11: cpu@11 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <11>;
> @@ -571,7 +571,7 @@ cpu12: cpu@12 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <12>;
> @@ -597,7 +597,7 @@ cpu13: cpu@13 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <13>;
> @@ -623,7 +623,7 @@ cpu14: cpu@14 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <14>;
> @@ -649,7 +649,7 @@ cpu15: cpu@15 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <15>;
> @@ -675,7 +675,7 @@ cpu16: cpu@16 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <16>;
> @@ -701,7 +701,7 @@ cpu17: cpu@17 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <17>;
> @@ -727,7 +727,7 @@ cpu18: cpu@18 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <18>;
> @@ -753,7 +753,7 @@ cpu19: cpu@19 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <19>;
> @@ -779,7 +779,7 @@ cpu20: cpu@20 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <20>;
> @@ -805,7 +805,7 @@ cpu21: cpu@21 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <21>;
> @@ -831,7 +831,7 @@ cpu22: cpu@22 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <22>;
> @@ -857,7 +857,7 @@ cpu23: cpu@23 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <23>;
> @@ -883,7 +883,7 @@ cpu24: cpu@24 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <24>;
> @@ -909,7 +909,7 @@ cpu25: cpu@25 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <25>;
> @@ -935,7 +935,7 @@ cpu26: cpu@26 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <26>;
> @@ -961,7 +961,7 @@ cpu27: cpu@27 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <27>;
> @@ -987,7 +987,7 @@ cpu28: cpu@28 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <28>;
> @@ -1013,7 +1013,7 @@ cpu29: cpu@29 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <29>;
> @@ -1039,7 +1039,7 @@ cpu30: cpu@30 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <30>;
> @@ -1065,7 +1065,7 @@ cpu31: cpu@31 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <31>;
> @@ -1091,7 +1091,7 @@ cpu32: cpu@32 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <32>;
> @@ -1117,7 +1117,7 @@ cpu33: cpu@33 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <33>;
> @@ -1143,7 +1143,7 @@ cpu34: cpu@34 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <34>;
> @@ -1169,7 +1169,7 @@ cpu35: cpu@35 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <35>;
> @@ -1195,7 +1195,7 @@ cpu36: cpu@36 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <36>;
> @@ -1221,7 +1221,7 @@ cpu37: cpu@37 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <37>;
> @@ -1247,7 +1247,7 @@ cpu38: cpu@38 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <38>;
> @@ -1273,7 +1273,7 @@ cpu39: cpu@39 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <39>;
> @@ -1299,7 +1299,7 @@ cpu40: cpu@40 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <40>;
> @@ -1325,7 +1325,7 @@ cpu41: cpu@41 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <41>;
> @@ -1351,7 +1351,7 @@ cpu42: cpu@42 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <42>;
> @@ -1377,7 +1377,7 @@ cpu43: cpu@43 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <43>;
> @@ -1403,7 +1403,7 @@ cpu44: cpu@44 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <44>;
> @@ -1429,7 +1429,7 @@ cpu45: cpu@45 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <45>;
> @@ -1455,7 +1455,7 @@ cpu46: cpu@46 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <46>;
> @@ -1481,7 +1481,7 @@ cpu47: cpu@47 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <47>;
> @@ -1507,7 +1507,7 @@ cpu48: cpu@48 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <48>;
> @@ -1533,7 +1533,7 @@ cpu49: cpu@49 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <49>;
> @@ -1559,7 +1559,7 @@ cpu50: cpu@50 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <50>;
> @@ -1585,7 +1585,7 @@ cpu51: cpu@51 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <51>;
> @@ -1611,7 +1611,7 @@ cpu52: cpu@52 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <52>;
> @@ -1637,7 +1637,7 @@ cpu53: cpu@53 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <53>;
> @@ -1663,7 +1663,7 @@ cpu54: cpu@54 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <54>;
> @@ -1689,7 +1689,7 @@ cpu55: cpu@55 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <55>;
> @@ -1715,7 +1715,7 @@ cpu56: cpu@56 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <56>;
> @@ -1741,7 +1741,7 @@ cpu57: cpu@57 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <57>;
> @@ -1767,7 +1767,7 @@ cpu58: cpu@58 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <58>;
> @@ -1793,7 +1793,7 @@ cpu59: cpu@59 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <59>;
> @@ -1819,7 +1819,7 @@ cpu60: cpu@60 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <60>;
> @@ -1845,7 +1845,7 @@ cpu61: cpu@61 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <61>;
> @@ -1871,7 +1871,7 @@ cpu62: cpu@62 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <62>;
> @@ -1897,7 +1897,7 @@ cpu63: cpu@63 {
>  			riscv,isa = "rv64imafdc";
>  			riscv,isa-base = "rv64i";
>  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> -					       "zicntr", "zicsr", "zifencei",
> +					       "ziccrse", "zicntr", "zicsr", "zifencei",
>  					       "zihpm", "xtheadvector";
>  			thead,vlenb = <128>;
>  			reg = <63>;
> -- 
> 2.47.2
> 

^ permalink raw reply	[flat|nested] 12+ messages in thread

* Re: [PATCH 2/2] riscv: dts: sophgo: add ziccrse for sg2042
  2025-05-09 22:42   ` Inochi Amaoto
@ 2025-05-10  0:15     ` Inochi Amaoto
  0 siblings, 0 replies; 12+ messages in thread
From: Inochi Amaoto @ 2025-05-10  0:15 UTC (permalink / raw)
  To: Han Gao, devicetree
  Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Chen Wang,
	Inochi Amaoto, Paul Walmsley, Palmer Dabbelt, Albert Ou,
	Alexandre Ghiti, sophgo, linux-riscv, linux-kernel

On Sat, May 10, 2025 at 06:42:02AM +0800, Inochi Amaoto wrote:
> On Sat, May 10, 2025 at 06:11:23AM +0800, Han Gao wrote:
> > sg2042 support Ziccrse ISA extension [1].
> > 
> > Link: https://lore.kernel.org/all/20241103145153.105097-12-alexghiti@rivosinc.com/ [1]
> > 
> > Signed-off-by: Han Gao <rabenda.cn@gmail.com>
> > ---
> >  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi | 128 ++++++++++----------
> >  1 file changed, 64 insertions(+), 64 deletions(-)
> > 
> > diff --git a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > index 927e0260acbd..04a6875574bb 100644
> > --- a/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > +++ b/arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi
> > @@ -259,7 +259,7 @@ cpu0: cpu@0 {
> >  			riscv,isa = "rv64imafdc";
> >  			riscv,isa-base = "rv64i";
> >  			riscv,isa-extensions = "i", "m", "a", "f", "d", "c",
> > -					       "zicntr", "zicsr", "zifencei",
> > +					       "ziccrse", "zicntr", "zicsr", "zifencei",
> >  					       "zihpm", "xtheadvector";
> >  			thead,vlenb = <128>;
> >  			reg = <0>;
> 
> I prefer to keep the maximum 74 chars per line. I suggest wrapping
> the string. This apply to all the change of this file.
> 

So, I mistake something, please wrap the line with max 80 chars.

Regards,
Inochi

^ permalink raw reply	[flat|nested] 12+ messages in thread

end of thread, other threads:[~2025-05-13 21:25 UTC | newest]

Thread overview: 12+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2025-05-09 22:11 [PATCH 0/2] riscv: dts: sophgo: add more sg2042 isa extension support Han Gao
2025-05-09 22:11 ` [PATCH 1/2] riscv: dts: sophgo: Add xtheadvector to the sg2042 devicetree Han Gao
2025-05-13  1:19   ` Chen Wang
2025-05-13  4:47     ` Inochi Amaoto
2025-05-13  6:45     ` Han Gao
2025-05-13  8:06       ` Chen Wang
2025-05-13  9:13         ` Han Gao
2025-05-13 10:05           ` Chen Wang
2025-05-13 21:25             ` Charlie Jenkins
2025-05-09 22:11 ` [PATCH 2/2] riscv: dts: sophgo: add ziccrse for sg2042 Han Gao
2025-05-09 22:42   ` Inochi Amaoto
2025-05-10  0:15     ` Inochi Amaoto

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